Commit 79db7e1b authored Jan 02, 2020 by Jacob Pan Committed by Joerg Roedel Jan 07, 2020

iommu/vt-d: Match CPU and IOMMU paging mode

When setting up first level page tables for sharing with CPU, we need
to ensure IOMMU can support no less than the levels supported by the
CPU.

It is not adequate, as in the current code, to set up 5-level paging
in PASID entry First Level Paging Mode(FLPM) solely based on CPU.

Currently, intel_pasid_setup_first_level() is only used by native SVM
code which already checks paging mode matches. However, future use of
this helper function may not be limited to native SVM.
https://lkml.org/lkml/2019/11/18/1037



Fixes: 437f35e1 ("iommu/vt-d: Add first level page table interface")
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>

parent ff3dc652

drivers/iommu/intel-pasid.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -499,8 +499,16 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
		}

		#ifdef CONFIG_X86
		if (cpu_feature_enabled(X86_FEATURE_LA57))
		/* Both CPU and IOMMU paging mode need to match */
		if (cpu_feature_enabled(X86_FEATURE_LA57)) {
		if (cap_5lp_support(iommu->cap)) {
		pasid_set_flpm(pte, 1);
		} else {
		pr_err("VT-d has no 5-level paging support for CPU\n");
		pasid_clear_entry(pte);
		return -EINVAL;
		}
		}
		#endif /* CONFIG_X86 */

		pasid_set_domain_id(pte, did);

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