Commit 79b4df68 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson
Browse files

drm/i915: move more defs in intel_display_power.h 



Move over structures, enums and macros from intel_display.h and
i915_drv.h to have all the display PM defines in the same header.

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190531222409.9177-3-daniele.ceraolospurio@intel.com
parent 7645b19d

drivers/gpu/drm/i915/i915_drv.h

+0 −110
Original line number Diff line number Diff line
@@ -729,116 +729,6 @@ struct intel_ilk_power_mgmt { 
	int r_t;

};



struct drm_i915_private;

struct i915_power_well;



struct i915_power_well_ops {

	/*

	 * Synchronize the well's hw state to match the current sw state, for

	 * example enable/disable it based on the current refcount. Called

	 * during driver init and resume time, possibly after first calling

	 * the enable/disable handlers.

	 */

	void (*sync_hw)(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well);

	/*

	 * Enable the well and resources that depend on it (for example

	 * interrupts located on the well). Called after the 0->1 refcount

	 * transition.

	 */

	void (*enable)(struct drm_i915_private *dev_priv,

		       struct i915_power_well *power_well);

	/*

	 * Disable the well and resources that depend on it. Called after

	 * the 1->0 refcount transition.

	 */

	void (*disable)(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well);

	/* Returns the hw enabled state. */

	bool (*is_enabled)(struct drm_i915_private *dev_priv,

			   struct i915_power_well *power_well);

};



struct i915_power_well_regs {

	i915_reg_t bios;

	i915_reg_t driver;

	i915_reg_t kvmr;

	i915_reg_t debug;

};



/* Power well structure for haswell */

struct i915_power_well_desc {

	const char *name;

	bool always_on;

	u64 domains;

	/* unique identifier for this power well */

	enum i915_power_well_id id;

	/*

	 * Arbitraty data associated with this power well. Platform and power

	 * well specific.

	 */

	union {

		struct {

			/*

			 * request/status flag index in the PUNIT power well

			 * control/status registers.

			 */

			u8 idx;

		} vlv;

		struct {

			enum dpio_phy phy;

		} bxt;

		struct {

			const struct i915_power_well_regs *regs;

			/*

			 * request/status flag index in the power well

			 * constrol/status registers.

			 */

			u8 idx;

			/* Mask of pipes whose IRQ logic is backed by the pw */

			u8 irq_pipe_mask;

			/* The pw is backing the VGA functionality */

			bool has_vga:1;

			bool has_fuses:1;

			/*

			 * The pw is for an ICL+ TypeC PHY port in

			 * Thunderbolt mode.

			 */

			bool is_tc_tbt:1;

		} hsw;

	};

	const struct i915_power_well_ops *ops;

};



struct i915_power_well {

	const struct i915_power_well_desc *desc;

	/* power well enable/disable usage count */

	int count;

	/* cached hw enabled state */

	bool hw_enabled;

};



struct i915_power_domains {

	/*

	 * Power wells needed for initialization at driver init and suspend

	 * time are on. They are kept on until after the first modeset.

	 */

	bool initializing;

	bool display_core_suspended;

	int power_well_count;



	intel_wakeref_t wakeref;



	struct mutex lock;

	int domain_use_count[POWER_DOMAIN_NUM];



	struct delayed_work async_put_work;

	intel_wakeref_t async_put_wakeref;

	u64 async_put_domains[2];



	struct i915_power_well *power_wells;

};



#define MAX_L3_SLICES 2

struct intel_l3_parity {

	u32 *remap_info[MAX_L3_SLICES];

drivers/gpu/drm/i915/intel_display.h

+0 −82
Original line number Diff line number Diff line
@@ -220,64 +220,6 @@ enum aux_ch { 


#define aux_ch_name(a) ((a) + 'A')



enum intel_display_power_domain {

	POWER_DOMAIN_DISPLAY_CORE,

	POWER_DOMAIN_PIPE_A,

	POWER_DOMAIN_PIPE_B,

	POWER_DOMAIN_PIPE_C,

	POWER_DOMAIN_PIPE_A_PANEL_FITTER,

	POWER_DOMAIN_PIPE_B_PANEL_FITTER,

	POWER_DOMAIN_PIPE_C_PANEL_FITTER,

	POWER_DOMAIN_TRANSCODER_A,

	POWER_DOMAIN_TRANSCODER_B,

	POWER_DOMAIN_TRANSCODER_C,

	POWER_DOMAIN_TRANSCODER_EDP,

	POWER_DOMAIN_TRANSCODER_EDP_VDSC,

	POWER_DOMAIN_TRANSCODER_DSI_A,

	POWER_DOMAIN_TRANSCODER_DSI_C,

	POWER_DOMAIN_PORT_DDI_A_LANES,

	POWER_DOMAIN_PORT_DDI_B_LANES,

	POWER_DOMAIN_PORT_DDI_C_LANES,

	POWER_DOMAIN_PORT_DDI_D_LANES,

	POWER_DOMAIN_PORT_DDI_E_LANES,

	POWER_DOMAIN_PORT_DDI_F_LANES,

	POWER_DOMAIN_PORT_DDI_A_IO,

	POWER_DOMAIN_PORT_DDI_B_IO,

	POWER_DOMAIN_PORT_DDI_C_IO,

	POWER_DOMAIN_PORT_DDI_D_IO,

	POWER_DOMAIN_PORT_DDI_E_IO,

	POWER_DOMAIN_PORT_DDI_F_IO,

	POWER_DOMAIN_PORT_DSI,

	POWER_DOMAIN_PORT_CRT,

	POWER_DOMAIN_PORT_OTHER,

	POWER_DOMAIN_VGA,

	POWER_DOMAIN_AUDIO,

	POWER_DOMAIN_AUX_A,

	POWER_DOMAIN_AUX_B,

	POWER_DOMAIN_AUX_C,

	POWER_DOMAIN_AUX_D,

	POWER_DOMAIN_AUX_E,

	POWER_DOMAIN_AUX_F,

	POWER_DOMAIN_AUX_IO_A,

	POWER_DOMAIN_AUX_TBT1,

	POWER_DOMAIN_AUX_TBT2,

	POWER_DOMAIN_AUX_TBT3,

	POWER_DOMAIN_AUX_TBT4,

	POWER_DOMAIN_GMBUS,

	POWER_DOMAIN_MODESET,

	POWER_DOMAIN_GT_IRQ,

	POWER_DOMAIN_INIT,



	POWER_DOMAIN_NUM,

};



#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

#define POWER_DOMAIN_TRANSCODER(tran) \

	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \

	 (tran) + POWER_DOMAIN_TRANSCODER_A)



/* Used by dp and fdi links */

struct intel_link_m_n {

	u32 tu;
@@ -364,30 +306,6 @@ struct intel_link_m_n { 
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \

		for_each_if((intel_connector)->base.encoder == (__encoder))



#define for_each_power_domain(domain, mask)				\

	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\

		for_each_if(BIT_ULL(domain) & (mask))



#define for_each_power_well(__dev_priv, __power_well)				\

	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\

	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\

		(__dev_priv)->power_domains.power_well_count;		\

	     (__power_well)++)



#define for_each_power_well_reverse(__dev_priv, __power_well)			\

	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\

			      (__dev_priv)->power_domains.power_well_count - 1;	\

	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\

	     (__power_well)--)



#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\

	for_each_power_well(__dev_priv, __power_well)				\

		for_each_if((__power_well)->desc->domains & (__domain_mask))



#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \

	for_each_power_well_reverse(__dev_priv, __power_well)		        \

		for_each_if((__power_well)->desc->domains & (__domain_mask))



#define for_each_old_intel_plane_in_state(__state, plane, old_plane_state, __i) \

	for ((__i) = 0; \

	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \

drivers/gpu/drm/i915/intel_display_power.h

+192 −0
Original line number Diff line number Diff line
@@ -8,10 +8,202 @@ 


#include "intel_display.h"

#include "intel_runtime_pm.h"

#include "i915_reg.h"



struct drm_i915_private;

struct intel_encoder;



enum intel_display_power_domain {

	POWER_DOMAIN_DISPLAY_CORE,

	POWER_DOMAIN_PIPE_A,

	POWER_DOMAIN_PIPE_B,

	POWER_DOMAIN_PIPE_C,

	POWER_DOMAIN_PIPE_A_PANEL_FITTER,

	POWER_DOMAIN_PIPE_B_PANEL_FITTER,

	POWER_DOMAIN_PIPE_C_PANEL_FITTER,

	POWER_DOMAIN_TRANSCODER_A,

	POWER_DOMAIN_TRANSCODER_B,

	POWER_DOMAIN_TRANSCODER_C,

	POWER_DOMAIN_TRANSCODER_EDP,

	POWER_DOMAIN_TRANSCODER_EDP_VDSC,

	POWER_DOMAIN_TRANSCODER_DSI_A,

	POWER_DOMAIN_TRANSCODER_DSI_C,

	POWER_DOMAIN_PORT_DDI_A_LANES,

	POWER_DOMAIN_PORT_DDI_B_LANES,

	POWER_DOMAIN_PORT_DDI_C_LANES,

	POWER_DOMAIN_PORT_DDI_D_LANES,

	POWER_DOMAIN_PORT_DDI_E_LANES,

	POWER_DOMAIN_PORT_DDI_F_LANES,

	POWER_DOMAIN_PORT_DDI_A_IO,

	POWER_DOMAIN_PORT_DDI_B_IO,

	POWER_DOMAIN_PORT_DDI_C_IO,

	POWER_DOMAIN_PORT_DDI_D_IO,

	POWER_DOMAIN_PORT_DDI_E_IO,

	POWER_DOMAIN_PORT_DDI_F_IO,

	POWER_DOMAIN_PORT_DSI,

	POWER_DOMAIN_PORT_CRT,

	POWER_DOMAIN_PORT_OTHER,

	POWER_DOMAIN_VGA,

	POWER_DOMAIN_AUDIO,

	POWER_DOMAIN_AUX_A,

	POWER_DOMAIN_AUX_B,

	POWER_DOMAIN_AUX_C,

	POWER_DOMAIN_AUX_D,

	POWER_DOMAIN_AUX_E,

	POWER_DOMAIN_AUX_F,

	POWER_DOMAIN_AUX_IO_A,

	POWER_DOMAIN_AUX_TBT1,

	POWER_DOMAIN_AUX_TBT2,

	POWER_DOMAIN_AUX_TBT3,

	POWER_DOMAIN_AUX_TBT4,

	POWER_DOMAIN_GMBUS,

	POWER_DOMAIN_MODESET,

	POWER_DOMAIN_GT_IRQ,

	POWER_DOMAIN_INIT,



	POWER_DOMAIN_NUM,

};



#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)

#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \

		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)

#define POWER_DOMAIN_TRANSCODER(tran) \

	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \

	 (tran) + POWER_DOMAIN_TRANSCODER_A)



struct i915_power_well;



struct i915_power_well_ops {

	/*

	 * Synchronize the well's hw state to match the current sw state, for

	 * example enable/disable it based on the current refcount. Called

	 * during driver init and resume time, possibly after first calling

	 * the enable/disable handlers.

	 */

	void (*sync_hw)(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well);

	/*

	 * Enable the well and resources that depend on it (for example

	 * interrupts located on the well). Called after the 0->1 refcount

	 * transition.

	 */

	void (*enable)(struct drm_i915_private *dev_priv,

		       struct i915_power_well *power_well);

	/*

	 * Disable the well and resources that depend on it. Called after

	 * the 1->0 refcount transition.

	 */

	void (*disable)(struct drm_i915_private *dev_priv,

			struct i915_power_well *power_well);

	/* Returns the hw enabled state. */

	bool (*is_enabled)(struct drm_i915_private *dev_priv,

			   struct i915_power_well *power_well);

};



struct i915_power_well_regs {

	i915_reg_t bios;

	i915_reg_t driver;

	i915_reg_t kvmr;

	i915_reg_t debug;

};



/* Power well structure for haswell */

struct i915_power_well_desc {

	const char *name;

	bool always_on;

	u64 domains;

	/* unique identifier for this power well */

	enum i915_power_well_id id;

	/*

	 * Arbitraty data associated with this power well. Platform and power

	 * well specific.

	 */

	union {

		struct {

			/*

			 * request/status flag index in the PUNIT power well

			 * control/status registers.

			 */

			u8 idx;

		} vlv;

		struct {

			enum dpio_phy phy;

		} bxt;

		struct {

			const struct i915_power_well_regs *regs;

			/*

			 * request/status flag index in the power well

			 * constrol/status registers.

			 */

			u8 idx;

			/* Mask of pipes whose IRQ logic is backed by the pw */

			u8 irq_pipe_mask;

			/* The pw is backing the VGA functionality */

			bool has_vga:1;

			bool has_fuses:1;

			/*

			 * The pw is for an ICL+ TypeC PHY port in

			 * Thunderbolt mode.

			 */

			bool is_tc_tbt:1;

		} hsw;

	};

	const struct i915_power_well_ops *ops;

};



struct i915_power_well {

	const struct i915_power_well_desc *desc;

	/* power well enable/disable usage count */

	int count;

	/* cached hw enabled state */

	bool hw_enabled;

};



struct i915_power_domains {

	/*

	 * Power wells needed for initialization at driver init and suspend

	 * time are on. They are kept on until after the first modeset.

	 */

	bool initializing;

	bool display_core_suspended;

	int power_well_count;



	intel_wakeref_t wakeref;



	struct mutex lock;

	int domain_use_count[POWER_DOMAIN_NUM];



	struct delayed_work async_put_work;

	intel_wakeref_t async_put_wakeref;

	u64 async_put_domains[2];



	struct i915_power_well *power_wells;

};



#define for_each_power_domain(domain, mask)				\

	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\

		for_each_if(BIT_ULL(domain) & (mask))



#define for_each_power_well(__dev_priv, __power_well)				\

	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\

	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\

		(__dev_priv)->power_domains.power_well_count;		\

	     (__power_well)++)



#define for_each_power_well_reverse(__dev_priv, __power_well)			\

	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\

			      (__dev_priv)->power_domains.power_well_count - 1;	\

	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\

	     (__power_well)--)



#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\

	for_each_power_well(__dev_priv, __power_well)				\

		for_each_if((__power_well)->desc->domains & (__domain_mask))



#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \

	for_each_power_well_reverse(__dev_priv, __power_well)		        \

		for_each_if((__power_well)->desc->domains & (__domain_mask))



void skl_enable_dc6(struct drm_i915_private *dev_priv);

void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);

void bxt_enable_dc9(struct drm_i915_private *dev_priv);

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