Commit 798a496b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'octeontx2-af-Debugfs-support-and-updates-to-parser-profile' 



Sunil Goutham says:

====================
octeontx2-af: Debugfs support and updates to parser profile

This patchset adds debugfs support to dump various HW state machine info
which helps in debugging issues. Info includes
- Current queue context, stats, resource utilization etc
- MCAM entry utilization, miss and pkt drop counter
- CGX ingress and egress stats
- Current RVU block allocation status
- etc.

Rest patches has changes wrt
- Updated packet parsing profile for parsing more protocols.
- RSS algorithms to include inner protocols while generating hash
- Handle current version of silicon's limitations wrt shaping, coloring
  and fixed mapping of transmit limiter queue's configuration.
- Enable broadcast packet replication to PF and it's VFs.
- Support for configurable NDC cache waymask
- etc

Changes from v1:
   Removed inline keyword for newly introduced APIs in few patches.
   - Suggested by David Miller.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b37fa92e a7faa68b

drivers/net/ethernet/marvell/octeontx2/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -16,3 +16,12 @@ config OCTEONTX2_AF 
	  Unit's admin function manager which manages all RVU HW resources

	  and provides a medium to other PF/VFs to configure HW. Should be

	  enabled for other RVU device drivers to work.



config NDC_DIS_DYNAMIC_CACHING

	bool "Disable caching of dynamic entries in NDC"

	depends on OCTEONTX2_AF

	default n

	---help---

	  This config option disables caching of dynamic entries such as NIX SQEs

	  , NPA stack pages etc in NDC. Also locks down NIX SQ/CQ/RQ/RSS and

	  NPA Aura/Pool contexts.

drivers/net/ethernet/marvell/octeontx2/af/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,4 +8,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o 


octeontx2_mbox-y := mbox.o

octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \

		  rvu_reg.o rvu_npc.o
 
		  rvu_reg.o rvu_npc.o rvu_debugfs.o

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+60 −0
Original line number Diff line number Diff line
@@ -138,6 +138,16 @@ void *cgx_get_pdata(int cgx_id) 
}

EXPORT_SYMBOL(cgx_get_pdata);



int cgx_get_cgxid(void *cgxd)

{

	struct cgx *cgx = cgxd;



	if (!cgx)

		return -EINVAL;



	return cgx->cgx_id;

}



/* Ensure the required lock for event queue(where asynchronous events are

 * posted) is acquired before calling this API. Else an asynchronous event(with

 * latest link status) can reach the destination before this function returns
@@ -281,6 +291,35 @@ void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable) 
}

EXPORT_SYMBOL(cgx_lmac_promisc_config);



/* Enable or disable forwarding received pause frames to Tx block */

void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable)

{

	struct cgx *cgx = cgxd;

	u64 cfg;



	if (!cgx)

		return;



	if (enable) {

		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);

		cfg |= CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;

		cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);



		cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);

		cfg |= CGX_SMUX_RX_FRM_CTL_CTL_BCK;

		cgx_write(cgx, lmac_id,	CGXX_SMUX_RX_FRM_CTL, cfg);

	} else {

		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);

		cfg &= ~CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK;

		cgx_write(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL, cfg);



		cfg = cgx_read(cgx, lmac_id, CGXX_SMUX_RX_FRM_CTL);

		cfg &= ~CGX_SMUX_RX_FRM_CTL_CTL_BCK;

		cgx_write(cgx, lmac_id,	CGXX_SMUX_RX_FRM_CTL, cfg);

	}

}

EXPORT_SYMBOL(cgx_lmac_enadis_rx_pause_fwding);



int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat)

{

	struct cgx *cgx = cgxd;
@@ -321,6 +360,27 @@ int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable) 
}

EXPORT_SYMBOL(cgx_lmac_rx_tx_enable);



int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable)

{

	struct cgx *cgx = cgxd;

	u64 cfg, last;



	if (!cgx || lmac_id >= cgx->lmac_count)

		return -ENODEV;



	cfg = cgx_read(cgx, lmac_id, CGXX_CMRX_CFG);

	last = cfg;

	if (enable)

		cfg |= DATA_PKT_TX_EN;

	else

		cfg &= ~DATA_PKT_TX_EN;



	if (cfg != last)

		cgx_write(cgx, lmac_id, CGXX_CMRX_CFG, cfg);

	return !!(last & DATA_PKT_TX_EN);

}

EXPORT_SYMBOL(cgx_lmac_tx_enable);



/* CGX Firmware interface low level support */

static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac)

{

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+13 −0
Original line number Diff line number Diff line
@@ -56,6 +56,11 @@ 
#define CGXX_GMP_PCS_MRX_CTL		0x30000

#define CGXX_GMP_PCS_MRX_CTL_LBK	BIT_ULL(14)



#define CGXX_SMUX_RX_FRM_CTL		0x20020

#define CGX_SMUX_RX_FRM_CTL_CTL_BCK	BIT_ULL(3)

#define CGXX_GMP_GMI_RXX_FRM_CTL	0x38028

#define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK	BIT_ULL(3)



#define CGX_COMMAND_REG			CGXX_SCRATCH1_REG

#define CGX_EVENT_REG			CGXX_SCRATCH0_REG

#define CGX_CMD_TIMEOUT			2200 /* msecs */
@@ -63,6 +68,11 @@ 
#define CGX_NVEC			37

#define CGX_LMAC_FWI			0



enum  cgx_nix_stat_type {

	NIX_STATS_RX,

	NIX_STATS_TX,

};



enum LMAC_TYPE {

	LMAC_MODE_SGMII		= 0,

	LMAC_MODE_XAUI		= 1,
@@ -96,6 +106,7 @@ struct cgx_event_cb { 
extern struct pci_driver cgx_driver;



int cgx_get_cgxcnt_max(void);

int cgx_get_cgxid(void *cgxd);

int cgx_get_lmac_cnt(void *cgxd);

void *cgx_get_pdata(int cgx_id);

int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
@@ -104,9 +115,11 @@ int cgx_lmac_evh_unregister(void *cgxd, int lmac_id); 
int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);

int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);

int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);

int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);

int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);

u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);

void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);

void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);

int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);

int cgx_get_link_info(void *cgxd, int lmac_id,

		      struct cgx_link_user_info *linfo);

drivers/net/ethernet/marvell/octeontx2/af/common.h

+16 −0
Original line number Diff line number Diff line
@@ -196,4 +196,20 @@ enum nix_scheduler { 
#define DEFAULT_RSS_CONTEXT_GROUP	0

#define MAX_RSS_INDIR_TBL_SIZE		256 /* 1 << Max adder bits */



/* NDC info */

enum ndc_idx_e {

	NIX0_RX = 0x0,

	NIX0_TX = 0x1,

	NPA0_U  = 0x2,

};



enum ndc_ctype_e {

	CACHING = 0x0,

	BYPASS = 0x1,

};



#define NDC_MAX_PORT 6

#define NDC_READ_TRANS 0

#define NDC_WRITE_TRANS 1



#endif /* COMMON_H */

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