Commit 79887142 authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: move align_mask and nop into ring funcs as well (v2) 



They are constant as well.

v2: update uvd and vce phys ring structures as well

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21cd942e

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c

+9 −10
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) 
{

	/* Align requested size with padding so unlock_commit can

	 * pad safely */

	ndw = (ndw + ring->align_mask) & ~ring->align_mask;

	ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;



	/* Make sure we aren't trying to allocate more space

	 * than the maximum for one submission
@@ -94,7 +94,7 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 
	int i;



	for (i = 0; i < count; i++)

		amdgpu_ring_write(ring, ring->nop);

		amdgpu_ring_write(ring, ring->funcs->nop);

}



/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
@@ -106,8 +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 
 */

void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)

{

	while (ib->length_dw & ring->align_mask)

		ib->ptr[ib->length_dw++] = ring->nop;

	while (ib->length_dw & ring->funcs->align_mask)

		ib->ptr[ib->length_dw++] = ring->funcs->nop;

}



/**
@@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) 
	uint32_t count;



	/* We pad to match fetch size */

	count = ring->align_mask + 1 - (ring->wptr & ring->align_mask);

	count %= ring->align_mask + 1;

	count = ring->funcs->align_mask + 1 -

		(ring->wptr & ring->funcs->align_mask);

	count %= ring->funcs->align_mask + 1;

	ring->funcs->insert_nop(ring, count);



	mb();
@@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) 
 * Returns 0 on success, error on failure.

 */

int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,

		     unsigned max_dw, u32 nop, u32 align_mask,

		     struct amdgpu_irq_src *irq_src, unsigned irq_type)

		     unsigned max_dw, struct amdgpu_irq_src *irq_src,

		     unsigned irq_type)

{

	int r;
@@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 


	ring->ring_size = roundup_pow_of_two(max_dw * 4 *

					     amdgpu_sched_hw_submission);

	ring->align_mask = align_mask;

	ring->nop = nop;



	/* Allocate ring buffer */

	if (ring->ring_obj == NULL) {

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+4 −4
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 
/* provided by hw blocks that expose a ring buffer for commands */

struct amdgpu_ring_funcs {

	enum amdgpu_ring_type	type;

	uint32_t		align_mask;

	u32			nop;



	/* ring read/write ptr handling */

	u32 (*get_rptr)(struct amdgpu_ring *ring);
@@ -149,10 +151,8 @@ struct amdgpu_ring { 
	unsigned		max_dw;

	int			count_dw;

	uint64_t		gpu_addr;

	uint32_t		align_mask;

	uint32_t		ptr_mask;

	bool			ready;

	u32			nop;

	u32			idx;

	u32			me;

	u32			pipe;
@@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 
void amdgpu_ring_commit(struct amdgpu_ring *ring);

void amdgpu_ring_undo(struct amdgpu_ring *ring);

int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,

		     unsigned ring_size, u32 nop, u32 align_mask,

		     struct amdgpu_irq_src *irq_src, unsigned irq_type);

		     unsigned ring_size, struct amdgpu_irq_src *irq_src,

		     unsigned irq_type);

void amdgpu_ring_fini(struct amdgpu_ring *ring);



#endif

drivers/gpu/drm/amd/amdgpu/cik_sdma.c

+4 −3
Original line number Diff line number Diff line
@@ -206,10 +206,10 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 


	for (i = 0; i < count; i++)

		if (sdma && sdma->burst_nop && (i == 0))

			amdgpu_ring_write(ring, ring->nop |

			amdgpu_ring_write(ring, ring->funcs->nop |

					  SDMA_NOP_COUNT(count - 1));

		else

			amdgpu_ring_write(ring, ring->nop);

			amdgpu_ring_write(ring, ring->funcs->nop);

}



/**
@@ -943,7 +943,6 @@ static int cik_sdma_sw_init(void *handle) 
		ring->ring_obj = NULL;

		sprintf(ring->name, "sdma%d", i);

		r = amdgpu_ring_init(adev, ring, 1024,

				     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,

				     &adev->sdma.trap_irq,

				     (i == 0) ?

				     AMDGPU_SDMA_IRQ_TRAP0 :
@@ -1210,6 +1209,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { 


static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {

	.type = AMDGPU_RING_TYPE_SDMA,

	.align_mask = 0xf,

	.nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),

	.get_rptr = cik_sdma_ring_get_rptr,

	.get_wptr = cik_sdma_ring_get_wptr,

	.set_wptr = cik_sdma_ring_set_wptr,

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

+4 −2
Original line number Diff line number Diff line
@@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) 
		ring->ring_obj = NULL;

		sprintf(ring->name, "gfx");

		r = amdgpu_ring_init(adev, ring, 1024,

				     0x80000000, 0xff,

				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);

		if (r)

			return r;
@@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) 
		sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);

		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;

		r = amdgpu_ring_init(adev, ring, 1024,

				     0x80000000, 0xff,

				     &adev->gfx.eop_irq, irq_type);

		if (r)

			return r;
@@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { 


static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {

	.type = AMDGPU_RING_TYPE_GFX,

	.align_mask = 0xff,

	.nop = 0x80000000,

	.get_rptr = gfx_v6_0_ring_get_rptr,

	.get_wptr = gfx_v6_0_ring_get_wptr,

	.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
@@ -3252,6 +3252,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { 


static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {

	.type = AMDGPU_RING_TYPE_COMPUTE,

	.align_mask = 0xff,

	.nop = 0x80000000,

	.get_rptr = gfx_v6_0_ring_get_rptr,

	.get_wptr = gfx_v6_0_ring_get_wptr,

	.set_wptr = gfx_v6_0_ring_set_wptr_compute,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+4 −2
Original line number Diff line number Diff line
@@ -4611,7 +4611,6 @@ static int gfx_v7_0_sw_init(void *handle) 
		ring->ring_obj = NULL;

		sprintf(ring->name, "gfx");

		r = amdgpu_ring_init(adev, ring, 1024,

				     PACKET3(PACKET3_NOP, 0x3FFF), 0xff,

				     &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);

		if (r)

			return r;
@@ -4637,7 +4636,6 @@ static int gfx_v7_0_sw_init(void *handle) 
		irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;

		/* type-2 packets are deprecated on MEC, use type-3 instead */

		r = amdgpu_ring_init(adev, ring, 1024,

				     PACKET3(PACKET3_NOP, 0x3FFF), 0xff,

				     &adev->gfx.eop_irq, irq_type);

		if (r)

			return r;
@@ -5108,6 +5106,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { 


static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {

	.type = AMDGPU_RING_TYPE_GFX,

	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.get_rptr = gfx_v7_0_ring_get_rptr,

	.get_wptr = gfx_v7_0_ring_get_wptr_gfx,

	.set_wptr = gfx_v7_0_ring_set_wptr_gfx,
@@ -5136,6 +5136,8 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { 


static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {

	.type = AMDGPU_RING_TYPE_COMPUTE,

	.align_mask = 0xff,

	.nop = PACKET3(PACKET3_NOP, 0x3FFF),

	.get_rptr = gfx_v7_0_ring_get_rptr,

	.get_wptr = gfx_v7_0_ring_get_wptr_compute,

	.set_wptr = gfx_v7_0_ring_set_wptr_compute,

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