Commit 796c2b35 authored by Liviu Dudau's avatar Liviu Dudau
Browse files

arm64: Add DT support for Juno r1 board. 



This board is based on Juno r0 with updated Cortex A5x revisions
and board errata fixes. It also contains coherent ThinLinks ports
on the expansion slot that allow for an AXI master on the daughter
card to participate in a coherency domain.

Support for SoC PCIe host bridge will be added as a separate series.

Signed-off-by: default avatarLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: default avatarJon Medhurst <tixy@linaro.org>
Acked-by: default avatarSudeep Holla <sudeep.holla@arm.com>
parent 9e6f374f

arch/arm64/boot/dts/arm/Makefile

+1 −1
Original line number Diff line number Diff line 
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb



always		:= $(dtb-y)

arch/arm64/boot/dts/arm/juno-r1.dts

0 → 100644
+116 −0
Original line number Diff line number Diff line 
/*

 * ARM Ltd. Juno Platform

 *

 * Copyright (c) 2015 ARM Ltd.

 *

 * This file is licensed under a dual GPLv2 or BSD license.

 */



/dts-v1/;



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	model = "ARM Juno development board (r1)";

	compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		serial0 = &soc_uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	psci {

		compatible = "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		A57_0: cpu@0 {

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

		};



		A57_1: cpu@1 {

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x0 0x1>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A57_L2>;

		};



		A53_0: cpu@100 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

		};



		A53_1: cpu@101 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x101>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

		};



		A53_2: cpu@102 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x102>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

		};



		A53_3: cpu@103 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x0 0x103>;

			device_type = "cpu";

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

		};



		A57_L2: l2-cache0 {

			compatible = "cache";

		};



		A53_L2: l2-cache1 {

			compatible = "cache";

		};

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&A57_0>,

				     <&A57_1>,

				     <&A53_0>,

				     <&A53_1>,

				     <&A53_2>,

				     <&A53_3>;

	};



	#include "juno-base.dtsi"



};



&memtimer {

	status = "okay";

};

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