drm/radeon: add accessors of pif_phy indirect register space (792edd69) · Commits · 戴 / test

drivers/gpu/drm/radeon/evergreen_reg.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -29,6 +29,11 @@
		#define TN_SMC_IND_DATA_0 0x204

		/* evergreen */
		#define EVERGREEN_PIF_PHY0_INDEX 0x8
		#define EVERGREEN_PIF_PHY0_DATA 0xc
		#define EVERGREEN_PIF_PHY1_INDEX 0x10
		#define EVERGREEN_PIF_PHY1_DATA 0x14

		#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
		#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
		#define EVERGREEN_D3VGA_CONTROL 0x3e0

+34 −0

Original line number	Diff line number	Diff line
		@@ -2087,6 +2087,10 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v);
		#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
		#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
		#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
		#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
		#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
		#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
		#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
		#define WREG32_P(reg, val, mask) \
		do { \
		uint32_t tmp_ = RREG32(reg); \
		@@ -2173,6 +2177,36 @@ static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		WREG32(EVERGREEN_CG_IND_DATA, (v));
		}

		static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
		{
		u32 r;

		WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		r = RREG32(EVERGREEN_PIF_PHY0_DATA);
		return r;
		}

		static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		{
		WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
		WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
		}

		static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
		{
		u32 r;

		WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		r = RREG32(EVERGREEN_PIF_PHY1_DATA);
		return r;
		}

		static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
		{
		WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
		WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
		}

		void r100_pll_errata_after_index(struct radeon_device *rdev);