Commit 78975f23 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'i2c/for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux 

Pull i2c updates from Wolfram Sang:

 - Peter Rosin did some major rework on the locking of i2c muxes by
   seperating parent-locked muxes and mux-locked muxes.

   This avoids deadlocks/workarounds when the mux itself needs i2c
   commands for muxing.  And as a side-effect, other workarounds in the
   media layer could be eliminated.  Also, Peter stepped up as the i2c
   mux maintainer and will keep an eye on these changes.

 - major updates to the octeon driver

 - add a helper to the core to generate the address+rw_bit octal and
   make drivers use it

 - quite a bunch of driver updates

* 'i2c/for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (84 commits)
  i2c: rcar: add DMA support
  i2c: st: Implement bus clear
  i2c: only check scl functions when using generic recovery
  i2c: algo-bit: declare i2c_bit_quirk_no_clk_stretch as static
  i2c: tegra: disable clock before returning error
  [media] rtl2832: regmap is aware of lockdep, drop local locking hack
  [media] rtl2832_sdr: get rid of empty regmap wrappers
  [media] rtl2832: change the i2c gate to be mux-locked
  [media] si2168: change the i2c gate to be mux-locked
  iio: imu: inv_mpu6050: change the i2c gate to be mux-locked
  i2c: mux: document i2c muxes and elaborate on parent-/mux-locked muxes
  i2c: mux: relax locking of the top i2c adapter during mux-locked muxing
  i2c: muxes always lock the parent adapter
  i2c: allow adapter drivers to override the adapter locking
  i2c: uniphier: add "\n" at the end of error log
  i2c: mv64xxx: remove CONFIG_HAVE_CLK conditionals
  i2c: mv64xxx: use clk_{prepare_enable,disable_unprepare}
  i2c: mv64xxx: handle probe deferral for the clock
  i2c: mv64xxx: enable the driver on ARCH_MVEBU
  i2c: octeon: Add workaround for broken irqs on CN3860
  ...
parents feaa7cb5 73e8b052

Documentation/devicetree/bindings/i2c/i2c-octeon.txt

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@@ -4,6 +4,12 @@ 


  Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.



  or



  compatible: "cavium,octeon-7890-twsi"



  Compatibility with cn78XX SOCs.



- reg: The base address of the TWSI/I2C bus controller register bank.



- #address-cells: Must be <1>.

Documentation/devicetree/bindings/i2c/i2c-rcar.txt

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@@ -19,6 +19,9 @@ Optional properties: 
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this

  property indicates the default frequency 100 kHz.

- clocks: clock specifier.

- dmas: Must contain a list of two references to DMA specifiers, one for

  transmission, and one for reception.

- dma-names: Must contain a list of two DMA names, "tx" and "rx".



- i2c-scl-falling-time-ns: see i2c.txt

- i2c-scl-internal-delay-ns: see i2c.txt

Documentation/i2c/i2c-topology

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I2C topology

============



There are a couple of reasons for building more complex i2c topologies

than a straight-forward i2c bus with one adapter and one or more devices.



1. A mux may be needed on the bus to prevent address collisions.



2. The bus may be accessible from some external bus master, and arbitration

   may be needed to determine if it is ok to access the bus.



3. A device (particularly RF tuners) may want to avoid the digital noise

   from the i2c bus, at least most of the time, and sits behind a gate

   that has to be operated before the device can be accessed.



Etc



These constructs are represented as i2c adapter trees by Linux, where

each adapter has a parent adapter (except the root adapter) and zero or

more child adapters. The root adapter is the actual adapter that issues

i2c transfers, and all adapters with a parent are part of an "i2c-mux"

object (quoted, since it can also be an arbitrator or a gate).



Depending of the particular mux driver, something happens when there is

an i2c transfer on one of its child adapters. The mux driver can

obviously operate a mux, but it can also do arbitration with an external

bus master or open a gate. The mux driver has two operations for this,

select and deselect. select is called before the transfer and (the

optional) deselect is called after the transfer.





Locking

=======



There are two variants of locking available to i2c muxes, they can be

mux-locked or parent-locked muxes. As is evident from below, it can be

useful to know if a mux is mux-locked or if it is parent-locked. The

following list was correct at the time of writing:



In drivers/i2c/muxes/

i2c-arb-gpio-challenge    Parent-locked

i2c-mux-gpio              Normally parent-locked, mux-locked iff

                          all involved gpio pins are controlled by the

                          same i2c root adapter that they mux.

i2c-mux-pca9541           Parent-locked

i2c-mux-pca954x           Parent-locked

i2c-mux-pinctrl           Normally parent-locked, mux-locked iff

                          all involved pinctrl devices are controlled

                          by the same i2c root adapter that they mux.

i2c-mux-reg               Parent-locked



In drivers/iio/

imu/inv_mpu6050/          Mux-locked



In drivers/media/

dvb-frontends/m88ds3103   Parent-locked

dvb-frontends/rtl2830     Parent-locked

dvb-frontends/rtl2832     Mux-locked

dvb-frontends/si2168      Mux-locked

usb/cx231xx/              Parent-locked





Mux-locked muxes

----------------



Mux-locked muxes does not lock the entire parent adapter during the

full select-transfer-deselect transaction, only the muxes on the parent

adapter are locked. Mux-locked muxes are mostly interesting if the

select and/or deselect operations must use i2c transfers to complete

their tasks. Since the parent adapter is not fully locked during the

full transaction, unrelated i2c transfers may interleave the different

stages of the transaction. This has the benefit that the mux driver

may be easier and cleaner to implement, but it has some caveats.



ML1. If you build a topology with a mux-locked mux being the parent

     of a parent-locked mux, this might break the expectation from the

     parent-locked mux that the root adapter is locked during the

     transaction.



ML2. It is not safe to build arbitrary topologies with two (or more)

     mux-locked muxes that are not siblings, when there are address

     collisions between the devices on the child adapters of these

     non-sibling muxes.



     I.e. the select-transfer-deselect transaction targeting e.g. device

     address 0x42 behind mux-one may be interleaved with a similar

     operation targeting device address 0x42 behind mux-two. The

     intension with such a topology would in this hypothetical example

     be that mux-one and mux-two should not be selected simultaneously,

     but mux-locked muxes do not guarantee that in all topologies.



ML3. A mux-locked mux cannot be used by a driver for auto-closing

     gates/muxes, i.e. something that closes automatically after a given

     number (one, in most cases) of i2c transfers. Unrelated i2c transfers

     may creep in and close prematurely.



ML4. If any non-i2c operation in the mux driver changes the i2c mux state,

     the driver has to lock the root adapter during that operation.

     Otherwise garbage may appear on the bus as seen from devices

     behind the mux, when an unrelated i2c transfer is in flight during

     the non-i2c mux-changing operation.





Mux-locked Example

------------------



                   .----------.     .--------.

    .--------.     |   mux-   |-----| dev D1 |

    |  root  |--+--|  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  .--------.

                |  '----------'  '--| dev D2 |

                |  .--------.       '--------'

                '--| dev D3 |

                   '--------'



When there is an access to D1, this happens:



 1. Someone issues an i2c-transfer to D1.

 2. M1 locks muxes on its parent (the root adapter in this case).

 3. M1 calls ->select to ready the mux.

 4. M1 (presumably) does some i2c-transfers as part of its select.

    These transfers are normal i2c-transfers that locks the parent

    adapter.

 5. M1 feeds the i2c-transfer from step 1 to its parent adapter as a

    normal i2c-transfer that locks the parent adapter.

 6. M1 calls ->deselect, if it has one.

 7. Same rules as in step 4, but for ->deselect.

 8. M1 unlocks muxes on its parent.



This means that accesses to D2 are lockout out for the full duration

of the entire operation. But accesses to D3 are possibly interleaved

at any point.





Parent-locked muxes

-------------------



Parent-locked muxes lock the parent adapter during the full select-

transfer-deselect transaction. The implication is that the mux driver

has to ensure that any and all i2c transfers through that parent

adapter during the transaction are unlocked i2c transfers (using e.g.

__i2c_transfer), or a deadlock will follow. There are a couple of

caveats.



PL1. If you build a topology with a parent-locked mux being the child

     of another mux, this might break a possible assumption from the

     child mux that the root adapter is unused between its select op

     and the actual transfer (e.g. if the child mux is auto-closing

     and the parent mux issus i2c-transfers as part of its select).

     This is especially the case if the parent mux is mux-locked, but

     it may also happen if the parent mux is parent-locked.



PL2. If select/deselect calls out to other subsystems such as gpio,

     pinctrl, regmap or iio, it is essential that any i2c transfers

     caused by these subsystems are unlocked. This can be convoluted to

     accomplish, maybe even impossible if an acceptably clean solution

     is sought.





Parent-locked Example

---------------------



                   .----------.     .--------.

    .--------.     |  parent- |-----| dev D1 |

    |  root  |--+--|  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  .--------.

                |  '----------'  '--| dev D2 |

                |  .--------.       '--------'

                '--| dev D3 |

                   '--------'



When there is an access to D1, this happens:



 1. Someone issues an i2c-transfer to D1.

 2. M1 locks muxes on its parent (the root adapter in this case).

 3. M1 locks its parent adapter.

 4. M1 calls ->select to ready the mux.

 5. If M1 does any i2c-transfers (on this root adapter) as part of

    its select, those transfers must be unlocked i2c-transfers so

    that they do not deadlock the root adapter.

 6. M1 feeds the i2c-transfer from step 1 to the root adapter as an

    unlocked i2c-transfer, so that it does not deadlock the parent

    adapter.

 7. M1 calls ->deselect, if it has one.

 8. Same rules as in step 5, but for ->deselect.

 9. M1 unlocks its parent adapter.

10. M1 unlocks muxes on its parent.





This means that accesses to both D2 and D3 are locked out for the full

duration of the entire operation.





Complex Examples

================



Parent-locked mux as parent of parent-locked mux

------------------------------------------------



This is a useful topology, but it can be bad.



                   .----------.     .----------.     .--------.

    .--------.     |  parent- |-----|  parent- |-----| dev D1 |

    |  root  |--+--|  locked  |     |  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  |  mux M2  |--.  .--------.

                |  '----------'  |  '----------'  '--| dev D2 |

                |  .--------.    |  .--------.       '--------'

                '--| dev D4 |    '--| dev D3 |

                   '--------'       '--------'



When any device is accessed, all other devices are locked out for

the full duration of the operation (both muxes lock their parent,

and specifically when M2 requests its parent to lock, M1 passes

the buck to the root adapter).



This topology is bad if M2 is an auto-closing mux and M1->select

issues any unlocked i2c transfers on the root adapter that may leak

through and be seen by the M2 adapter, thus closing M2 prematurely.





Mux-locked mux as parent of mux-locked mux

------------------------------------------



This is a good topology.



                   .----------.     .----------.     .--------.

    .--------.     |   mux-   |-----|   mux-   |-----| dev D1 |

    |  root  |--+--|  locked  |     |  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  |  mux M2  |--.  .--------.

                |  '----------'  |  '----------'  '--| dev D2 |

                |  .--------.    |  .--------.       '--------'

                '--| dev D4 |    '--| dev D3 |

                   '--------'       '--------'



When device D1 is accessed, accesses to D2 are locked out for the

full duration of the operation (muxes on the top child adapter of M1

are locked). But accesses to D3 and D4 are possibly interleaved at

any point. Accesses to D3 locks out D1 and D2, but accesses to D4

are still possibly interleaved.





Mux-locked mux as parent of parent-locked mux

---------------------------------------------



This is probably a bad topology.



                   .----------.     .----------.     .--------.

    .--------.     |   mux-   |-----|  parent- |-----| dev D1 |

    |  root  |--+--|  locked  |     |  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  |  mux M2  |--.  .--------.

                |  '----------'  |  '----------'  '--| dev D2 |

                |  .--------.    |  .--------.       '--------'

                '--| dev D4 |    '--| dev D3 |

                   '--------'       '--------'



When device D1 is accessed, accesses to D2 and D3 are locked out

for the full duration of the operation (M1 locks child muxes on the

root adapter). But accesses to D4 are possibly interleaved at any

point.



This kind of topology is generally not suitable and should probably

be avoided. The reason is that M2 probably assumes that there will

be no i2c transfers during its calls to ->select and ->deselect, and

if there are, any such transfers might appear on the slave side of M2

as partial i2c transfers, i.e. garbage or worse. This might cause

device lockups and/or other problems.



The topology is especially troublesome if M2 is an auto-closing

mux. In that case, any interleaved accesses to D4 might close M2

prematurely, as might any i2c-transfers part of M1->select.



But if M2 is not making the above stated assumption, and if M2 is not

auto-closing, the topology is fine.





Parent-locked mux as parent of mux-locked mux

---------------------------------------------



This is a good topology.



                   .----------.     .----------.     .--------.

    .--------.     |  parent- |-----|   mux-   |-----| dev D1 |

    |  root  |--+--|  locked  |     |  locked  |     '--------'

    '--------'  |  |  mux M1  |--.  |  mux M2  |--.  .--------.

                |  '----------'  |  '----------'  '--| dev D2 |

                |  .--------.    |  .--------.       '--------'

                '--| dev D4 |    '--| dev D3 |

                   '--------'       '--------'



When D1 is accessed, accesses to D2 are locked out for the full

duration of the operation (muxes on the top child adapter of M1

are locked). Accesses to D3 and D4 are possibly interleaved at

any point, just as is expected for mux-locked muxes.



When D3 or D4 are accessed, everything else is locked out. For D3

accesses, M1 locks the root adapter. For D4 accesses, the root

adapter is locked directly.





Two mux-locked sibling muxes

----------------------------



This is a good topology.



                                    .--------.

                   .----------.  .--| dev D1 |

                   |   mux-   |--'  '--------'

                .--|  locked  |     .--------.

                |  |  mux M1  |-----| dev D2 |

                |  '----------'     '--------'

                |  .----------.     .--------.

    .--------.  |  |   mux-   |-----| dev D3 |

    |  root  |--+--|  locked  |     '--------'

    '--------'  |  |  mux M2  |--.  .--------.

                |  '----------'  '--| dev D4 |

                |  .--------.       '--------'

                '--| dev D5 |

                   '--------'



When D1 is accessed, accesses to D2, D3 and D4 are locked out. But

accesses to D5 may be interleaved at any time.





Two parent-locked sibling muxes

-------------------------------



This is a good topology.



                                   .--------.

                   .----------.  .--| dev D1 |

                   |  parent- |--'  '--------'

                .--|  locked  |     .--------.

                |  |  mux M1  |-----| dev D2 |

                |  '----------'     '--------'

                |  .----------.     .--------.

    .--------.  |  |  parent- |-----| dev D3 |

    |  root  |--+--|  locked  |     '--------'

    '--------'  |  |  mux M2  |--.  .--------.

                |  '----------'  '--| dev D4 |

                |  .--------.       '--------'

                '--| dev D5 |

                   '--------'



When any device is accessed, accesses to all other devices are locked

out.





Mux-locked and parent-locked sibling muxes

------------------------------------------



This is a good topology.



                                   .--------.

                   .----------.  .--| dev D1 |

                   |   mux-   |--'  '--------'

                .--|  locked  |     .--------.

                |  |  mux M1  |-----| dev D2 |

                |  '----------'     '--------'

                |  .----------.     .--------.

    .--------.  |  |  parent- |-----| dev D3 |

    |  root  |--+--|  locked  |     '--------'

    '--------'  |  |  mux M2  |--.  .--------.

                |  '----------'  '--| dev D4 |

                |  .--------.       '--------'

                '--| dev D5 |

                   '--------'



When D1 or D2 are accessed, accesses to D3 and D4 are locked out while

accesses to D5 may interleave. When D3 or D4 are accessed, accesses to

all other devices are locked out.

MAINTAINERS

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@@ -5348,6 +5348,7 @@ I2C MUXES 
M:	Peter Rosin <peda@axentia.se>

L:	linux-i2c@vger.kernel.org

S:	Maintained

F:	Documentation/i2c/i2c-topology

F:	Documentation/i2c/muxes/

F:	Documentation/devicetree/bindings/i2c/i2c-mux*

F:	drivers/i2c/i2c-mux.c

drivers/i2c/algos/i2c-algo-bit.c

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@@ -617,7 +617,7 @@ const struct i2c_algorithm i2c_bit_algo = { 
};

EXPORT_SYMBOL(i2c_bit_algo);



const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = {

static const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = {

	.flags = I2C_AQ_NO_CLK_STRETCH,

};

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