Commit 788f07eb authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2019-04-11' of... 

Merge tag 'drm-intel-fixes-2019-04-11' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Revert back to max link rate and lane count on eDP.
- DSI related fixes for all platforms including Ice Lake.
- GVT Fixes including one vGPU display plane size regression fix,
one for preventing use-after-free in ppgtt shadow free function,
and another warning fix for iomem access annotation.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190411235832.GA6476@intel.com
parents ffb5d6fe 3f5f5d53

drivers/gpu/drm/i915/gvt/dmabuf.c

+6 −3
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_vgpu_primary_plane_format p;

	struct intel_vgpu_cursor_plane_format c;

	int ret;

	int ret, tile_height = 1;



	if (plane_id == DRM_PLANE_TYPE_PRIMARY) {

		ret = intel_vgpu_decode_primary_plane(vgpu, &p);
@@ -228,12 +228,15 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
			break;

		case PLANE_CTL_TILED_X:

			info->drm_format_mod = I915_FORMAT_MOD_X_TILED;

			tile_height = 8;

			break;

		case PLANE_CTL_TILED_Y:

			info->drm_format_mod = I915_FORMAT_MOD_Y_TILED;

			tile_height = 32;

			break;

		case PLANE_CTL_TILED_YF:

			info->drm_format_mod = I915_FORMAT_MOD_Yf_TILED;

			tile_height = 32;

			break;

		default:

			gvt_vgpu_err("invalid tiling mode: %x\n", p.tiled);
@@ -264,8 +267,8 @@ static int vgpu_get_plane_info(struct drm_device *dev, 
		return -EINVAL;

	}



	info->size = (info->stride * info->height + PAGE_SIZE - 1)

		      >> PAGE_SHIFT;

	info->size = (info->stride * roundup(info->height, tile_height)

		      + PAGE_SIZE - 1) >> PAGE_SHIFT;

	if (info->size == 0) {

		gvt_vgpu_err("fb size is zero\n");

		return -EINVAL;

drivers/gpu/drm/i915/gvt/gtt.c

+9 −3
Original line number Diff line number Diff line
@@ -750,14 +750,20 @@ static void ppgtt_free_spt(struct intel_vgpu_ppgtt_spt *spt) 


static void ppgtt_free_all_spt(struct intel_vgpu *vgpu)

{

	struct intel_vgpu_ppgtt_spt *spt;

	struct intel_vgpu_ppgtt_spt *spt, *spn;

	struct radix_tree_iter iter;

	void **slot;

	LIST_HEAD(all_spt);

	void __rcu **slot;



	rcu_read_lock();

	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {

		spt = radix_tree_deref_slot(slot);

		ppgtt_free_spt(spt);

		list_move(&spt->post_shadow_list, &all_spt);

	}

	rcu_read_unlock();



	list_for_each_entry_safe(spt, spn, &all_spt, post_shadow_list)

		ppgtt_free_spt(spt);

}



static int ppgtt_handle_guest_write_page_table_bytes(

drivers/gpu/drm/i915/gvt/kvmgt.c

+3 −3
Original line number Diff line number Diff line
@@ -905,7 +905,7 @@ static inline bool intel_vgpu_in_aperture(struct intel_vgpu *vgpu, u64 off) 
static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off,

		void *buf, unsigned long count, bool is_write)

{

	void *aperture_va;

	void __iomem *aperture_va;



	if (!intel_vgpu_in_aperture(vgpu, off) ||

	    !intel_vgpu_in_aperture(vgpu, off + count)) {
@@ -920,9 +920,9 @@ static int intel_vgpu_aperture_rw(struct intel_vgpu *vgpu, u64 off, 
		return -EIO;



	if (is_write)

		memcpy(aperture_va + offset_in_page(off), buf, count);

		memcpy_toio(aperture_va + offset_in_page(off), buf, count);

	else

		memcpy(buf, aperture_va + offset_in_page(off), count);

		memcpy_fromio(buf, aperture_va + offset_in_page(off), count);



	io_mapping_unmap(aperture_va);

drivers/gpu/drm/i915/icl_dsi.c

+27 −21
Original line number Diff line number Diff line
@@ -323,6 +323,21 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) 
	}

}



static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,

				     struct intel_dsi *intel_dsi)

{

	enum port port;



	for_each_dsi_port(port, intel_dsi->ports) {

		WARN_ON(intel_dsi->io_wakeref[port]);

		intel_dsi->io_wakeref[port] =

			intel_display_power_get(dev_priv,

						port == PORT_A ?

						POWER_DOMAIN_PORT_DDI_A_IO :

						POWER_DOMAIN_PORT_DDI_B_IO);

	}

}



static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -336,13 +351,7 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 
		I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);

	}



	for_each_dsi_port(port, intel_dsi->ports) {

		intel_dsi->io_wakeref[port] =

			intel_display_power_get(dev_priv,

						port == PORT_A ?

						POWER_DOMAIN_PORT_DDI_A_IO :

						POWER_DOMAIN_PORT_DDI_B_IO);

	}

	get_dsi_io_power_domains(dev_priv, intel_dsi);

}



static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
@@ -589,6 +598,12 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, 
		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);

	}

	I915_WRITE(DPCLKA_CFGCR0_ICL, val);



	for_each_dsi_port(port, intel_dsi->ports) {

		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);

	}

	I915_WRITE(DPCLKA_CFGCR0_ICL, val);



	POSTING_READ(DPCLKA_CFGCR0_ICL);



	mutex_unlock(&dev_priv->dpll_lock);
@@ -1117,7 +1132,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) 
			DRM_ERROR("DDI port:%c buffer not idle\n",

				  port_name(port));

	}

	gen11_dsi_ungate_clocks(encoder);

	gen11_dsi_gate_clocks(encoder);

}



static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
@@ -1218,20 +1233,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder, 
	return 0;

}



static u64 gen11_dsi_get_power_domains(struct intel_encoder *encoder,

static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,

					struct intel_crtc_state *crtc_state)

{

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);

	u64 domains = 0;

	enum port port;



	for_each_dsi_port(port, intel_dsi->ports)

		if (port == PORT_A)

			domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO);

		else

			domains |= BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO);



	return domains;

	get_dsi_io_power_domains(to_i915(encoder->base.dev),

				 enc_to_intel_dsi(&encoder->base));

}



static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,

drivers/gpu/drm/i915/intel_ddi.c

+11 −12
Original line number Diff line number Diff line
@@ -2075,12 +2075,11 @@ intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) 
					      intel_aux_power_domain(dig_port);

}



static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder,

static void intel_ddi_get_power_domains(struct intel_encoder *encoder,

					struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_digital_port *dig_port;

	u64 domains;



	/*

	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -2088,10 +2087,10 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder, 
	 * hook.

	 */

	if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))

		return 0;

		return;



	dig_port = enc_to_dig_port(&encoder->base);

	domains = BIT_ULL(dig_port->ddi_io_power_domain);

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);



	/*

	 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
@@ -2099,15 +2098,15 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder, 
	 */

	if (intel_crtc_has_dp_encoder(crtc_state) ||

	    intel_port_is_tc(dev_priv, encoder->port))

		domains |= BIT_ULL(intel_ddi_main_link_aux_domain(dig_port));

		intel_display_power_get(dev_priv,

					intel_ddi_main_link_aux_domain(dig_port));



	/*

	 * VDSC power is needed when DSC is enabled

	 */

	if (crtc_state->dsc_params.compression_enable)

		domains |= BIT_ULL(intel_dsc_power_domain(crtc_state));



	return domains;

		intel_display_power_get(dev_priv,

					intel_dsc_power_domain(crtc_state));

}



void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
@@ -2825,10 +2824,10 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) 
				return;

		}

		/*

		 * DSI ports should have their DDI clock ungated when disabled

		 * and gated when enabled.

		 * For DSI we keep the ddi clocks gated

		 * except during enable/disable sequence.

		 */

		ddi_clk_needed = !encoder->base.crtc;

		ddi_clk_needed = false;

	}



	val = I915_READ(DPCLKA_CFGCR0_ICL);

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