Commit 78814465 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
Browse files

MIPS: Alchemy: Stop IRQ name sharing 



Eliminate the sharing of IRQ names among the differenct Alchemy
variants.  IRQ numbers need no longer be hidden behind a
CONFIG_SOC_AU1XXX symbol: step 1 in my quest to make the Alchemy
code less reliant on a hardcoded subtype.

This patch also renames the GPIO irq number constants. It's really
an interrupt line, NOT a GPIO number!

Code which relied on certain irq numbers to have the same name
across all supported cpu subtypes is changed to determine current
cpu subtype at runtime; in some places this isn't possible so
a "compat" symbol is used.

Run-tested on DB1200.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 93e9cd84

arch/mips/alchemy/common/dbdma.c

+36 −25
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ 
 *

 */



#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/slab.h>

#include <linux/spinlock.h>
@@ -58,7 +59,6 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); 


static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;

static int dbdma_initialized;

static void au1xxx_dbdma_init(void);



static dbdev_tab_t dbdev_tab[] = {

#ifdef CONFIG_SOC_AU1550
@@ -250,8 +250,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, 
	 * which can't be done successfully during board set up.

	 */

	if (!dbdma_initialized)

		au1xxx_dbdma_init();

	dbdma_initialized = 1;

		return 0;



	stp = find_dbdev_id(srcid);

	if (stp == NULL)
@@ -871,28 +870,6 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) 
	return IRQ_RETVAL(1);

}



static void au1xxx_dbdma_init(void)

{

	int irq_nr;



	dbdma_gptr->ddma_config = 0;

	dbdma_gptr->ddma_throttle = 0;

	dbdma_gptr->ddma_inten = 0xffff;

	au_sync();



#if defined(CONFIG_SOC_AU1550)

	irq_nr = AU1550_DDMA_INT;

#elif defined(CONFIG_SOC_AU1200)

	irq_nr = AU1200_DDMA_INT;

#else

	#error Unknown Au1x00 SOC

#endif



	if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,

			"Au1xxx dbdma", (void *)dbdma_gptr))

		printk(KERN_ERR "Can't get 1550 dbdma irq");

}



void au1xxx_dbdma_dump(u32 chanid)

{

	chan_tab_t	 *ctp;
@@ -1041,4 +1018,38 @@ void au1xxx_dbdma_resume(void) 
	}

}

#endif	/* CONFIG_PM */



static int __init au1xxx_dbdma_init(void)

{

	int irq_nr, ret;



	dbdma_gptr->ddma_config = 0;

	dbdma_gptr->ddma_throttle = 0;

	dbdma_gptr->ddma_inten = 0xffff;

	au_sync();



	switch (alchemy_get_cputype()) {

	case ALCHEMY_CPU_AU1550:

		irq_nr = AU1550_DDMA_INT;

		break;

	case ALCHEMY_CPU_AU1200:

		irq_nr = AU1200_DDMA_INT;

		break;

	default:

		return -ENODEV;

	}



	ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,

			"Au1xxx dbdma", (void *)dbdma_gptr);

	if (ret)

		printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");

	else {

		dbdma_initialized = 1;

		printk(KERN_INFO "Alchemy DBDMA initialized\n");

	}



	return ret;

}

subsys_initcall(au1xxx_dbdma_init);



#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */

arch/mips/alchemy/common/dma.c

+31 −5
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
 *  675 Mass Ave, Cambridge, MA 02139, USA.

 *

 */



#include <linux/init.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/errno.h>
@@ -188,17 +190,14 @@ int request_au1000_dma(int dev_id, const char *dev_str, 
		dev = &dma_dev_table[dev_id];



	if (irqhandler) {

		chan->irq = AU1000_DMA_INT_BASE + i;

		chan->irq_dev = irq_dev_id;

		ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,

				  chan->irq_dev);

		if (ret) {

			chan->irq = 0;

			chan->irq_dev = NULL;

			return ret;

		}

	} else {

		chan->irq = 0;

		chan->irq_dev = NULL;

	}
@@ -226,13 +225,40 @@ void free_au1000_dma(unsigned int dmanr) 
	}



	disable_dma(dmanr);

	if (chan->irq)

	if (chan->irq_dev)

		free_irq(chan->irq, chan->irq_dev);



	chan->irq = 0;

	chan->irq_dev = NULL;

	chan->dev_id = -1;

}

EXPORT_SYMBOL(free_au1000_dma);



static int __init au1000_dma_init(void)

{

        int base, i;



        switch (alchemy_get_cputype()) {

        case ALCHEMY_CPU_AU1000:

                base = AU1000_DMA_INT_BASE;

                break;

        case ALCHEMY_CPU_AU1500:

                base = AU1500_DMA_INT_BASE;

                break;

        case ALCHEMY_CPU_AU1100:

                base = AU1100_DMA_INT_BASE;

                break;

        default:

                goto out;

        }



        for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)

                au1000_dma_table[i].irq = base + i;



        printk(KERN_INFO "Alchemy DMA initialized\n");



out:

        return 0;

}

arch_initcall(au1000_dma_init);



#endif /* AU1000 AU1500 AU1100 */

arch/mips/alchemy/common/irq.c

+146 −144
Original line number Diff line number Diff line
@@ -88,34 +88,34 @@ struct au1xxx_irqmap { 
#elif defined(CONFIG_SOC_AU1500)



	{ AU1500_UART0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1500_PCI_INTA,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1500_PCI_INTB,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1500_UART3_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },

	{ AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_PCI_INTC,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1500_PCI_INTD,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1500_DMA_INT_BASE,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_TOY_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_RTC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },

	{ AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_USB_HOST_INT,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1500_ACSYNC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1500_MAC1_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1500_AC97C_INT,	  IRQ_TYPE_EDGE_RISING, 0 },



#elif defined(CONFIG_SOC_AU1100)
@@ -123,33 +123,33 @@ struct au1xxx_irqmap { 
	{ AU1100_UART1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_SD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_UART3_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },

	{ AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 1 },

	{ AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },

	{ AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_SSI0_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_SSI1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_TOY_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_RTC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1100_IRDA_TX_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_IRDA_RX_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },

	{ AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_USB_HOST_INT,	  IRQ_TYPE_LEVEL_LOW,   0 },

	{ AU1100_ACSYNC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_MAC0_DMA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1100_LCD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1100_AC97C_INT,	  IRQ_TYPE_EDGE_RISING, 0 },



#elif defined(CONFIG_SOC_AU1550)
@@ -167,14 +167,14 @@ struct au1xxx_irqmap { 
	{ AU1550_PSC1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1550_PSC2_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1550_PSC3_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1550_TOY_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_RTC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1550_NAND_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },

	{ AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
@@ -195,14 +195,14 @@ struct au1xxx_irqmap { 
	{ AU1200_PSC1_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1200_AES_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1200_CAMERA_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1200_TOY_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_RTC_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },

	{ AU1200_NAND_INT,	  IRQ_TYPE_EDGE_RISING, 0 },

	{ AU1200_USB_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },

	{ AU1200_LCD_INT,	  IRQ_TYPE_LEVEL_HIGH,  0 },
@@ -316,7 +316,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr) 
 * nowhere in the current kernel sources is it disabled.	--mlau

 */

#if defined(CONFIG_MIPS_PB1000)

	if (irq_nr == AU1000_GPIO_15)

	if (irq_nr == AU1000_GPIO15_INT)

		au_writel(0x4000, PB1000_MDR); /* enable int */

#endif

	au_sync();
@@ -388,11 +388,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr) 


static int au1x_ic1_setwake(unsigned int irq, unsigned int on)

{

	unsigned int bit = irq - AU1000_INTC1_INT_BASE;

	int bit = irq - AU1000_INTC1_INT_BASE;

	unsigned long wakemsk, flags;



	/* only GPIO 0-7 can act as wakeup source: */

	if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))

	/* only GPIO 0-7 can act as wakeup source.  Fortunately these

	 * are wired up identically on all supported variants.

	 */

	if ((bit < 0) || (bit > 7))

		return -EINVAL;



	local_irq_save(flags);

arch/mips/alchemy/common/platform.c

+4 −4
Original line number Diff line number Diff line
@@ -73,8 +73,8 @@ static struct resource au1xxx_usb_ohci_resources[] = { 
		.flags		= IORESOURCE_MEM,

	},

	[1] = {

		.start		= AU1000_USB_HOST_INT,

		.end		= AU1000_USB_HOST_INT,

		.start		= FOR_PLATFORM_C_USB_HOST_INT,

		.end		= FOR_PLATFORM_C_USB_HOST_INT,

		.flags		= IORESOURCE_IRQ,

	},

};
@@ -132,8 +132,8 @@ static struct resource au1xxx_usb_ehci_resources[] = { 
		.flags		= IORESOURCE_MEM,

	},

	[1] = {

		.start		= AU1000_USB_HOST_INT,

		.end		= AU1000_USB_HOST_INT,

		.start		= AU1200_USB_INT,

		.end		= AU1200_USB_INT,

		.flags		= IORESOURCE_IRQ,

	},

};

arch/mips/alchemy/common/time.c

+30 −5
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>

 * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>

 *

 * Previous incarnations were:

 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
@@ -85,7 +85,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { 
	.name		= "rtcmatch2",

	.features	= CLOCK_EVT_FEAT_ONESHOT,

	.rating		= 100,

	.irq		= AU1000_RTC_MATCH2_INT,

	.set_next_event	= au1x_rtcmatch2_set_next_event,

	.set_mode	= au1x_rtcmatch2_set_mode,

	.cpumask	= cpu_all_mask,
@@ -98,11 +97,13 @@ static struct irqaction au1x_rtcmatch2_irqaction = { 
	.dev_id		= &au1x_rtcmatch2_clockdev,

};



void __init plat_time_init(void)

static int __init alchemy_time_init(unsigned int m2int)

{

	struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;

	unsigned long t;



	au1x_rtcmatch2_clockdev.irq = m2int;



	/* Check if firmware (YAMON, ...) has enabled 32kHz and clock

	 * has been detected.  If so install the rtcmatch2 clocksource,

	 * otherwise don't bother.  Note that both bits being set is by
@@ -148,13 +149,18 @@ void __init plat_time_init(void) 
	cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);

	cd->min_delta_ns = clockevent_delta2ns(8, cd);	/* ~0.25ms */

	clockevents_register_device(cd);

	setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);

	setup_irq(m2int, &au1x_rtcmatch2_irqaction);



	printk(KERN_INFO "Alchemy clocksource installed\n");



	return;

	return 0;



cntr_err:

	return -1;

}



static void __init alchemy_setup_c0timer(void)

{

	/*

	 * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this

	 * function is called.  Because the Alchemy counters are unusable
@@ -166,3 +172,22 @@ cntr_err: 
	r4k_clockevent_init();

	init_r4k_clocksource();

}



static int alchemy_m2inttab[] __initdata = {

	AU1000_RTC_MATCH2_INT,

	AU1500_RTC_MATCH2_INT,

	AU1100_RTC_MATCH2_INT,

	AU1550_RTC_MATCH2_INT,

	AU1200_RTC_MATCH2_INT,

};



void __init plat_time_init(void)

{

	int t;



	t = alchemy_get_cputype();

	if (t == ALCHEMY_CPU_UNKNOWN)

		alchemy_setup_c0timer();

	else if (alchemy_time_init(alchemy_m2inttab[t]))

		alchemy_setup_c0timer();

}

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