MIPS: SGI-IP27: Only reserve interrupts used in Linux

#ifndef __ASM_SN_INTR_H

#define __ASM_SN_INTR_H

/* Number of interrupt levels associated with each interrupt register. */

#define N_INTPEND_BITS		64

#define INT_PEND0_BASELVL	0

#define INT_PEND1_BASELVL	64

#define N_INTPENDJUNK_BITS	8

#define INTPENDJUNK_CLRBIT	0x80

/*

 * Macros to manipulate the interrupt register on the calling hub chip.

 */

#define CPU_RESCHED_B_IRQ	 8

#define CPU_CALL_A_IRQ		 9

#define CPU_CALL_B_IRQ		10

#define MSC_MESG_INTR		11

#define BASE_PCI_IRQ		12

/*

 * INT_PEND0 again, bits determined by hardware / hardcoded:

 */

#define SDISK_INTR		63	/* SABLE name */

#define IP_PEND0_6_63		63	/* What is this bit? */

/*

 * INT_PEND1 hard-coded bits:

	 * Mark these as reserved right away so they won't be used accidentally

	 * later.

	 */

	for (i = 0; i <= BASE_PCI_IRQ; i++)

	for (i = 0; i <= CPU_CALL_B_IRQ; i++)

		set_bit(i, hub_irq_map);

	set_bit(IP_PEND0_6_63, hub_irq_map);

	for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++)

		set_bit(i, hub_irq_map);