Commit 783d3186 authored by Marc Zyngier's avatar Marc Zyngier Committed by Jason Cooper
Browse files

irqchip: crossbar: Convert dra7 crossbar to stacked domains 



Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.

Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.

Unfortunately, as the DT bindings failed to acknowledge the
fact that this is actually yet another interrupt controller
(the third, actually), we have yet another breakage. Oh well.

Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1426088629-15377-3-git-send-email-marc.zyngier@arm.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 08b55e2a

arch/arm/boot/dts/am57xx-beagle-x15.dts

+1 −2
Original line number Diff line number Diff line
@@ -454,7 +454,6 @@ 
	mcp_rtc: rtc@6f {

		compatible = "microchip,mcp7941x";

		reg = <0x6f>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>;  /* IRQ_SYS_1N */



		pinctrl-names = "default";
@@ -477,7 +476,7 @@ 


&uart3 {

	status = "okay";

	interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,

			      <&dra7_pmx_core 0x248>;



	pinctrl-names = "default";

arch/arm/boot/dts/dra7-evm.dts

+1 −1
Original line number Diff line number Diff line
@@ -446,7 +446,7 @@ 
	status = "okay";

	pinctrl-names = "default";

	pinctrl-0 = <&uart1_pins>;

	interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

	interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

			      <&dra7_pmx_core 0x3e0>;

};

arch/arm/boot/dts/dra7.dtsi

+19 −16
Original line number Diff line number Diff line
@@ -13,14 +13,13 @@ 
#include "skeleton.dtsi"



#define MAX_SOURCES 400

#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	compatible = "ti,dra7xx";

	interrupt-parent = <&gic>;

	interrupt-parent = <&crossbar_mpu>;



	aliases {

		i2c0 = &i2c1;
@@ -50,18 +49,19 @@ 
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

	};



	gic: interrupt-controller@48211000 {

		compatible = "arm,cortex-a15-gic";

		interrupt-controller;

		#interrupt-cells = <3>;

		arm,routable-irqs = <192>;

		reg = <0x48211000 0x1000>,

		      <0x48212000 0x1000>,

		      <0x48214000 0x2000>,

		      <0x48216000 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;

		interrupt-parent = <&gic>;

	};



	/*
@@ -91,8 +91,8 @@ 
		ti,hwmods = "l3_main_1", "l3_main_2";

		reg = <0x44000000 0x1000000>,

		      <0x45000000 0x1000>;

		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;

		interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

				      <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;



		prm: prm@4ae06000 {

			compatible = "ti,dra7-prm";
@@ -344,7 +344,7 @@ 
		uart1: serial@4806a000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806a000 0x100>;

			interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

			interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart1";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -355,7 +355,7 @@ 
		uart2: serial@4806c000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806c000 0x100>;

			interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart2";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -366,7 +366,7 @@ 
		uart3: serial@48020000 {

			compatible = "ti,omap4-uart";

			reg = <0x48020000 0x100>;

			interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart3";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -377,7 +377,7 @@ 
		uart4: serial@4806e000 {

			compatible = "ti,omap4-uart";

			reg = <0x4806e000 0x100>;

			interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart4";

			clock-frequency = <48000000>;

                        status = "disabled";
@@ -388,7 +388,7 @@ 
		uart5: serial@48066000 {

			compatible = "ti,omap4-uart";

			reg = <0x48066000 0x100>;

			interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart5";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -399,7 +399,7 @@ 
		uart6: serial@48068000 {

			compatible = "ti,omap4-uart";

			reg = <0x48068000 0x100>;

			interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart6";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -410,7 +410,7 @@ 
		uart7: serial@48420000 {

			compatible = "ti,omap4-uart";

			reg = <0x48420000 0x100>;

			interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart7";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -419,7 +419,7 @@ 
		uart8: serial@48422000 {

			compatible = "ti,omap4-uart";

			reg = <0x48422000 0x100>;

			interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart8";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -428,7 +428,7 @@ 
		uart9: serial@48424000 {

			compatible = "ti,omap4-uart";

			reg = <0x48424000 0x100>;

			interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart9";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -437,7 +437,7 @@ 
		uart10: serial@4ae2b000 {

			compatible = "ti,omap4-uart";

			reg = <0x4ae2b000 0x100>;

			interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "uart10";

			clock-frequency = <48000000>;

			status = "disabled";
@@ -1337,9 +1337,12 @@ 
			status = "disabled";

		};



		crossbar_mpu: crossbar@4a020000 {

		crossbar_mpu: crossbar@4a002a48 {

			compatible = "ti,irq-crossbar";

			reg = <0x4a002a48 0x130>;

			interrupt-controller;

			interrupt-parent = <&gic>;

			#interrupt-cells = <3>;

			ti,max-irqs = <160>;

			ti,max-crossbar-sources = <MAX_SOURCES>;

			ti,reg-size = <2>;

arch/arm/boot/dts/dra72-evm.dts

+0 −1
Original line number Diff line number Diff line
@@ -160,7 +160,6 @@ 
		pinctrl-0 = <&tps65917_pins_default>;



		interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */

		interrupt-parent = <&gic>;

		interrupt-controller;

		#interrupt-cells = <2>;

arch/arm/boot/dts/dra72x.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


	pmu {

		compatible = "arm,cortex-a15-pmu";

		interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

	};

};

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