Commit 7825aeb7 authored by Jianqun Xu's avatar Jianqun Xu Committed by Linus Walleij
Browse files

pinctrl: rockchip: add rk3308 SoC support 



This patch do support pinctrl for RK3308 SoCs.

Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarJianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20191015091708.7934-3-jay.xu@rock-chips.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent e54349ed

drivers/pinctrl/pinctrl-rockchip.c

+381 −1
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ enum rockchip_pinctrl_type { 
	RK3128,

	RK3188,

	RK3288,

	RK3308,

	RK3368,

	RK3399,

};
@@ -70,6 +71,7 @@ enum rockchip_pinctrl_type { 
#define IOMUX_SOURCE_PMU	BIT(2)

#define IOMUX_UNROUTED		BIT(3)

#define IOMUX_WIDTH_3BIT	BIT(4)

#define IOMUX_WIDTH_2BIT	BIT(5)



/**

 * @type: iomux variant using IOMUX_* constants
@@ -656,6 +658,100 @@ static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { 
	},

};



static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {

	{

		.num = 1,

		.pin = 14,

		.reg = 0x28,

		.bit = 12,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 15,

		.reg = 0x2c,

		.bit = 0,

		.mask = 0x3

	}, {

		.num = 1,

		.pin = 18,

		.reg = 0x30,

		.bit = 4,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 19,

		.reg = 0x30,

		.bit = 8,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 20,

		.reg = 0x30,

		.bit = 12,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 21,

		.reg = 0x34,

		.bit = 0,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 22,

		.reg = 0x34,

		.bit = 4,

		.mask = 0xf

	}, {

		.num = 1,

		.pin = 23,

		.reg = 0x34,

		.bit = 8,

		.mask = 0xf

	}, {

		.num = 3,

		.pin = 12,

		.reg = 0x68,

		.bit = 8,

		.mask = 0xf

	}, {

		.num = 3,

		.pin = 13,

		.reg = 0x68,

		.bit = 12,

		.mask = 0xf

	}, {

		.num = 2,

		.pin = 2,

		.reg = 0x608,

		.bit = 0,

		.mask = 0x7

	}, {

		.num = 2,

		.pin = 3,

		.reg = 0x608,

		.bit = 4,

		.mask = 0x7

	}, {

		.num = 2,

		.pin = 16,

		.reg = 0x610,

		.bit = 8,

		.mask = 0x7

	}, {

		.num = 3,

		.pin = 10,

		.reg = 0x610,

		.bit = 0,

		.mask = 0x7

	}, {

		.num = 3,

		.pin = 11,

		.reg = 0x610,

		.bit = 4,

		.mask = 0x7

	},

};



static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {

	{

		.num = 2,
@@ -982,6 +1078,192 @@ static struct rockchip_mux_route_data rk3288_mux_route_data[] = { 
	},

};



static struct rockchip_mux_route_data rk3308_mux_route_data[] = {

	{

		/* rtc_clk */

		.bank_num = 0,

		.pin = 19,

		.func = 1,

		.route_offset = 0x314,

		.route_val = BIT(16 + 0) | BIT(0),

	}, {

		/* uart2_rxm0 */

		.bank_num = 1,

		.pin = 22,

		.func = 2,

		.route_offset = 0x314,

		.route_val = BIT(16 + 2) | BIT(16 + 3),

	}, {

		/* uart2_rxm1 */

		.bank_num = 4,

		.pin = 26,

		.func = 2,

		.route_offset = 0x314,

		.route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),

	}, {

		/* i2c3_sdam0 */

		.bank_num = 0,

		.pin = 15,

		.func = 2,

		.route_offset = 0x608,

		.route_val = BIT(16 + 8) | BIT(16 + 9),

	}, {

		/* i2c3_sdam1 */

		.bank_num = 3,

		.pin = 12,

		.func = 2,

		.route_offset = 0x608,

		.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),

	}, {

		/* i2c3_sdam2 */

		.bank_num = 2,

		.pin = 0,

		.func = 3,

		.route_offset = 0x608,

		.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),

	}, {

		/* i2s-8ch-1-sclktxm0 */

		.bank_num = 1,

		.pin = 3,

		.func = 2,

		.route_offset = 0x308,

		.route_val = BIT(16 + 3),

	}, {

		/* i2s-8ch-1-sclkrxm0 */

		.bank_num = 1,

		.pin = 4,

		.func = 2,

		.route_offset = 0x308,

		.route_val = BIT(16 + 3),

	}, {

		/* i2s-8ch-1-sclktxm1 */

		.bank_num = 1,

		.pin = 13,

		.func = 2,

		.route_offset = 0x308,

		.route_val = BIT(16 + 3) | BIT(3),

	}, {

		/* i2s-8ch-1-sclkrxm1 */

		.bank_num = 1,

		.pin = 14,

		.func = 2,

		.route_offset = 0x308,

		.route_val = BIT(16 + 3) | BIT(3),

	}, {

		/* pdm-clkm0 */

		.bank_num = 1,

		.pin = 4,

		.func = 3,

		.route_offset = 0x308,

		.route_val =  BIT(16 + 12) | BIT(16 + 13),

	}, {

		/* pdm-clkm1 */

		.bank_num = 1,

		.pin = 14,

		.func = 4,

		.route_offset = 0x308,

		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),

	}, {

		/* pdm-clkm2 */

		.bank_num = 2,

		.pin = 6,

		.func = 2,

		.route_offset = 0x308,

		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),

	}, {

		/* pdm-clkm-m2 */

		.bank_num = 2,

		.pin = 4,

		.func = 3,

		.route_offset = 0x600,

		.route_val = BIT(16 + 2) | BIT(2),

	}, {

		/* spi1_miso */

		.bank_num = 3,

		.pin = 10,

		.func = 3,

		.route_offset = 0x314,

		.route_val = BIT(16 + 9),

	}, {

		/* spi1_miso_m1 */

		.bank_num = 2,

		.pin = 4,

		.func = 2,

		.route_offset = 0x314,

		.route_val = BIT(16 + 9) | BIT(9),

	}, {

		/* owire_m0 */

		.bank_num = 0,

		.pin = 11,

		.func = 3,

		.route_offset = 0x314,

		.route_val = BIT(16 + 10) | BIT(16 + 11),

	}, {

		/* owire_m1 */

		.bank_num = 1,

		.pin = 22,

		.func = 7,

		.route_offset = 0x314,

		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),

	}, {

		/* owire_m2 */

		.bank_num = 2,

		.pin = 2,

		.func = 5,

		.route_offset = 0x314,

		.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),

	}, {

		/* can_rxd_m0 */

		.bank_num = 0,

		.pin = 11,

		.func = 2,

		.route_offset = 0x314,

		.route_val = BIT(16 + 12) | BIT(16 + 13),

	}, {

		/* can_rxd_m1 */

		.bank_num = 1,

		.pin = 22,

		.func = 5,

		.route_offset = 0x314,

		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),

	}, {

		/* can_rxd_m2 */

		.bank_num = 2,

		.pin = 2,

		.func = 4,

		.route_offset = 0x314,

		.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),

	}, {

		/* mac_rxd0_m0 */

		.bank_num = 1,

		.pin = 20,

		.func = 3,

		.route_offset = 0x314,

		.route_val = BIT(16 + 14),

	}, {

		/* mac_rxd0_m1 */

		.bank_num = 4,

		.pin = 2,

		.func = 2,

		.route_offset = 0x314,

		.route_val = BIT(16 + 14) | BIT(14),

	}, {

		/* uart3_rx */

		.bank_num = 3,

		.pin = 12,

		.func = 4,

		.route_offset = 0x314,

		.route_val = BIT(16 + 15),

	}, {

		/* uart3_rx_m1 */

		.bank_num = 0,

		.pin = 17,

		.func = 3,

		.route_offset = 0x314,

		.route_val = BIT(16 + 15) | BIT(15),

	},

};



static struct rockchip_mux_route_data rk3328_mux_route_data[] = {

	{

		/* uart2dbg_rxm0 */
@@ -1475,6 +1757,26 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, 
	return 0;

}



#define RK3308_SCHMITT_PINS_PER_REG		8

#define RK3308_SCHMITT_BANK_STRIDE		16

#define RK3308_SCHMITT_GRF_OFFSET		0x1a0



static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,

				    int pin_num, struct regmap **regmap,

				    int *reg, u8 *bit)

{

	struct rockchip_pinctrl *info = bank->drvdata;



	*regmap = info->regmap_base;

	*reg = RK3308_SCHMITT_GRF_OFFSET;



	*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;

	*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);

	*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;



	return 0;

}



#define RK2928_PULL_OFFSET		0x118

#define RK2928_PULL_PINS_PER_REG	16

#define RK2928_PULL_BANK_STRIDE		8
@@ -1646,6 +1948,40 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, 
	*bit *= RK3288_DRV_BITS_PER_PIN;

}



#define RK3308_PULL_OFFSET		0xa0



static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,

				    int pin_num, struct regmap **regmap,

				    int *reg, u8 *bit)

{

	struct rockchip_pinctrl *info = bank->drvdata;



	*regmap = info->regmap_base;

	*reg = RK3308_PULL_OFFSET;

	*reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;

	*reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);



	*bit = (pin_num % RK3188_PULL_PINS_PER_REG);

	*bit *= RK3188_PULL_BITS_PER_PIN;

}



#define RK3308_DRV_GRF_OFFSET		0x100



static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,

				    int pin_num, struct regmap **regmap,

				    int *reg, u8 *bit)

{

	struct rockchip_pinctrl *info = bank->drvdata;



	*regmap = info->regmap_base;

	*reg = RK3308_DRV_GRF_OFFSET;

	*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;

	*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);



	*bit = (pin_num % RK3288_DRV_PINS_PER_REG);

	*bit *= RK3288_DRV_BITS_PER_PIN;

}



#define RK3368_PULL_GRF_OFFSET		0x100

#define RK3368_PULL_PMU_OFFSET		0x10
@@ -1986,6 +2322,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 
	case RV1108:

	case RK3188:

	case RK3288:

	case RK3308:

	case RK3368:

	case RK3399:

		pull_type = bank->pull_type[pin_num / 8];
@@ -2030,6 +2367,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, 
	case RV1108:

	case RK3188:

	case RK3288:

	case RK3308:

	case RK3368:

	case RK3399:

		pull_type = bank->pull_type[pin_num / 8];
@@ -2293,6 +2631,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 
	case RV1108:

	case RK3188:

	case RK3288:

	case RK3308:

	case RK3368:

	case RK3399:

		return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
@@ -3303,7 +3642,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( 
			 * 4bit iomux'es are spread over two registers.

			 */

			inc = (iom->type & (IOMUX_WIDTH_4BIT |

					    IOMUX_WIDTH_3BIT)) ? 8 : 4;

					    IOMUX_WIDTH_3BIT |

					    IOMUX_WIDTH_2BIT)) ? 8 : 4;

			if (iom->type & IOMUX_SOURCE_PMU)

				pmu_offs += inc;

			else
@@ -3709,6 +4049,44 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = { 
		.drv_calc_reg		= rk3288_calc_drv_reg_and_bit,

};



static struct rockchip_pin_bank rk3308_pin_banks[] = {

	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT),

	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT),

	PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT),

	PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT),

	PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT,

					     IOMUX_WIDTH_2BIT),

};



static struct rockchip_pin_ctrl rk3308_pin_ctrl = {

		.pin_banks		= rk3308_pin_banks,

		.nr_banks		= ARRAY_SIZE(rk3308_pin_banks),

		.label			= "RK3308-GPIO",

		.type			= RK3308,

		.grf_mux_offset		= 0x0,

		.iomux_recalced		= rk3308_mux_recalced_data,

		.niomux_recalced	= ARRAY_SIZE(rk3308_mux_recalced_data),

		.iomux_routes		= rk3308_mux_route_data,

		.niomux_routes		= ARRAY_SIZE(rk3308_mux_route_data),

		.pull_calc_reg		= rk3308_calc_pull_reg_and_bit,

		.drv_calc_reg		= rk3308_calc_drv_reg_and_bit,

		.schmitt_calc_reg	= rk3308_calc_schmitt_reg_and_bit,

};



static struct rockchip_pin_bank rk3328_pin_banks[] = {

	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),

	PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
@@ -3849,6 +4227,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = { 
		.data = &rk3228_pin_ctrl },

	{ .compatible = "rockchip,rk3288-pinctrl",

		.data = &rk3288_pin_ctrl },

	{ .compatible = "rockchip,rk3308-pinctrl",

		.data = &rk3308_pin_ctrl },

	{ .compatible = "rockchip,rk3328-pinctrl",

		.data = &rk3328_pin_ctrl },

	{ .compatible = "rockchip,rk3368-pinctrl",

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