Commit 781a08d9 authored by Tudor Ambarus's avatar Tudor Ambarus Committed by Herbert Xu
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crypto: atmel-aes - Fix counter overflow in CTR mode 



32 bit counter is not supported by neither of our AES IPs, all implement
a 16 bit block counter. Drop the 32 bit block counter logic.

Fixes: fcac8365 ("crypto: atmel-aes - fix the counter overflow in CTR mode")
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent c65d1237

drivers/crypto/atmel-aes.c

+12 −25
Original line number Diff line number Diff line
@@ -88,7 +88,6 @@ 
struct atmel_aes_caps {

	bool			has_dualbuff;

	bool			has_cfb64;

	bool			has_ctr32;

	bool			has_gcm;

	bool			has_xts;

	bool			has_authenc;
@@ -1018,8 +1017,9 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) 
	struct atmel_aes_ctr_ctx *ctx = atmel_aes_ctr_ctx_cast(dd->ctx);

	struct skcipher_request *req = skcipher_request_cast(dd->areq);

	struct scatterlist *src, *dst;

	u32 ctr, blocks;

	size_t datalen;

	u32 ctr;

	u16 blocks, start, end;

	bool use_dma, fragmented = false;



	/* Check for transfer completion. */
@@ -1031,27 +1031,17 @@ static int atmel_aes_ctr_transfer(struct atmel_aes_dev *dd) 
	datalen = req->cryptlen - ctx->offset;

	blocks = DIV_ROUND_UP(datalen, AES_BLOCK_SIZE);

	ctr = be32_to_cpu(ctx->iv[3]);

	if (dd->caps.has_ctr32) {

		/* Check 32bit counter overflow. */

		u32 start = ctr;

		u32 end = start + blocks - 1;



		if (end < start) {

			ctr |= 0xffffffff;

			datalen = AES_BLOCK_SIZE * -start;

			fragmented = true;

		}

	} else {



	/* Check 16bit counter overflow. */

		u16 start = ctr & 0xffff;

		u16 end = start + (u16)blocks - 1;

	start = ctr & 0xffff;

	end = start + blocks - 1;



	if (blocks >> 16 || end < start) {

		ctr |= 0xffff;

		datalen = AES_BLOCK_SIZE * (0x10000 - start);

		fragmented = true;

	}

	}



	use_dma = (datalen >= ATMEL_AES_DMA_THRESHOLD);



	/* Jump to offset. */
@@ -2521,7 +2511,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) 
{

	dd->caps.has_dualbuff = 0;

	dd->caps.has_cfb64 = 0;

	dd->caps.has_ctr32 = 0;

	dd->caps.has_gcm = 0;

	dd->caps.has_xts = 0;

	dd->caps.has_authenc = 0;
@@ -2532,7 +2521,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) 
	case 0x500:

		dd->caps.has_dualbuff = 1;

		dd->caps.has_cfb64 = 1;

		dd->caps.has_ctr32 = 1;

		dd->caps.has_gcm = 1;

		dd->caps.has_xts = 1;

		dd->caps.has_authenc = 1;
@@ -2541,7 +2529,6 @@ static void atmel_aes_get_cap(struct atmel_aes_dev *dd) 
	case 0x200:

		dd->caps.has_dualbuff = 1;

		dd->caps.has_cfb64 = 1;

		dd->caps.has_ctr32 = 1;

		dd->caps.has_gcm = 1;

		dd->caps.max_burst_size = 4;

		break;

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