Commit 781885fd authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Jonathan Corbet
Browse files

docs: sh: convert register-banks.txt to ReST 



- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org


Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
parent 7539b417

Documentation/sh/index.rst

+1 −0
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@@ -8,6 +8,7 @@ SuperH Interfaces Guide 
    :maxdepth: 1



    new-machine

    register-banks



Memory Management

=================

Documentation/sh/register-banks.txt→Documentation/sh/register-banks.rst

+10 −3
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.. SPDX-License-Identifier: GPL-2.0



==========================================

Notes on register bank usage in the kernel

==========================================
@@ -23,11 +26,15 @@ Presently the kernel uses several of these registers. 


	- r0_bank, r1_bank (referenced as k0 and k1, used for scratch

	  registers when doing exception handling).



	- r2_bank (used to track the EXPEVT/INTEVT code)



		- Used by do_IRQ() and friends for doing irq mapping based off

		  of the interrupt exception vector jump table offset



	- r6_bank (global interrupt mask)



		- The SR.IMASK interrupt handler makes use of this to set the

		  interrupt priority level (used by local_irq_enable())

	- r7_bank (current)



	- r7_bank (current)

arch/sh/Kconfig.cpu

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@@ -85,7 +85,7 @@ config CPU_HAS_SR_RB 
	  that are lacking this bit must have another method in place for

	  accomplishing what is taken care of by the banked registers.



	  See <file:Documentation/sh/register-banks.txt> for further

	  See <file:Documentation/sh/register-banks.rst> for further

	  information on SR.RB and register banking in the kernel in general.



config CPU_HAS_PTEAEX

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