Commit 7800064b authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: Add basic dm816x device tree configuration 

Similar to other omap variants, let's add dm816x support.

Note that this is based on generated data from the
TI81XX-LINUX-PSP-04.04.00.02 patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html



I've verified the basic functionality, but have not been
able to test all the devices on dm8168-evm.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 7300bfff

arch/arm/boot/dts/dm816x.dtsi

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+386 −0
Original line number Diff line number Diff line 
/*

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/omap.h>



#include "skeleton.dtsi"



/ {

	compatible = "ti,dm816";

	interrupt-parent = <&intc>;



	aliases {

		i2c0 = &i2c1;

		i2c1 = &i2c2;

		serial0 = &uart1;

		serial1 = &uart2;

		serial2 = &uart3;

		ethernet0 = &eth0;

		ethernet1 = &eth1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu@0 {

			compatible = "arm,cortex-a8";

			device_type = "cpu";

			reg = <0>;

		};

	};



	pmu {

		compatible = "arm,cortex-a8-pmu";

		interrupts = <3>;

	};



	/*

	 * The soc node represents the soc top level view. It is used for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap3-mpu";

			ti,hwmods = "mpu";

		};

	};



	dm816x_pinmux: pinmux@44e10800 {

		compatible = "pinctrl-single";

		reg = <0x48140800 0x50a>;

		#address-cells = <1>;

		#size-cells = <0>;

		pinctrl-single,register-width = <16>;

		pinctrl-single,function-mask = <0xf>;

	};



	/*

	 * XXX: Use a flat representation of the dm816x interconnect.

	 * The real dm816x interconnect network is quite complex. Since

	 * it will not bring real advantage to represent that in DT

	 * for the moment, just use a fake OCP bus entry to represent

	 * the whole bus hierarchy.

	 */

	ocp {

		compatible = "ti,omap3-l3-smx", "simple-bus";

		reg = <0x44000000 0x10000>;

		interrupts = <9 10>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		ti,hwmods = "l3_main";



		prcm: prcm@48180000 {

			compatible = "ti,dm816-prcm";

			reg = <0x48180000 0x4000>;



			prcm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			prcm_clockdomains: clockdomains {

			};

		};



		scrm: scrm@48140000 {

			compatible = "ti,dm816-scrm";

			reg = <0x48140000 0x21000>;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x48140000 0x21000>;



			scrm_clocks: clocks {

				#address-cells = <1>;

				#size-cells = <0>;

			};



			scrm_clockdomains: clockdomains {

			};

		};



		cm: syscon@44e10000 {

			compatible = "ti,am33xx-controlmodule", "syscon";

			reg = <0x44e10000 0x800>;

		};



		edma: edma@49000000 {

			compatible = "ti,edma3";

			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";

			reg =   <0x49000000 0x10000>,

			        <0x44e10f90 0x40>;

			interrupts = <12 13 14>;

			#dma-cells = <1>;

		};



		elm: elm@48080000 {

			compatible = "ti,816-elm";

			ti,hwmods = "elm";

			reg = <0x48080000 0x2000>;

			interrupts = <4>;

		};



		gpio1: gpio@48032000 {

			compatible = "ti,omap3-gpio";

			ti,hwmods = "gpio1";

			reg = <0x48032000 0x1000>;

			interrupts = <97>;

		};



		gpio2: gpio@4804c000 {

			compatible = "ti,omap3-gpio";

			ti,hwmods = "gpio2";

			reg = <0x4804c000 0x1000>;

			interrupts = <99>;

		};



		gpmc: gpmc@50000000 {

			compatible = "ti,am3352-gpmc";

			ti,hwmods = "gpmc";

			reg = <0x50000000 0x2000>;

			#address-cells = <2>;

			#size-cells = <1>;

			interrupts = <100>;

			gpmc,num-cs = <6>;

			gpmc,num-waitpins = <2>;

		};



		i2c1: i2c@48028000 {

			compatible = "ti,omap4-i2c";

			ti,hwmods = "i2c1";

			reg = <0x48028000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <70>;

			dmas = <&edma 58 &edma 59>;

			dma-names = "tx", "rx";

		};



		i2c2: i2c@4802a000 {

			compatible = "ti,omap4-i2c";

			ti,hwmods = "i2c2";

			reg = <0x4802a000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <71>;

			dmas = <&edma 60 &edma 61>;

			dma-names = "tx", "rx";

		};



		intc: interrupt-controller@48200000 {

			compatible = "ti,dm816-intc";

			interrupt-controller;

			#interrupt-cells = <1>;

			reg = <0x48200000 0x1000>;

		};



		mailbox: mailbox@480c8000 {

			compatible = "ti,omap4-mailbox";

			reg = <0x480c8000 0x2000>;

			interrupts = <77>;

			ti,hwmods = "mailbox";

			ti,mbox-num-users = <4>;

			ti,mbox-num-fifos = <12>;

			mbox_dsp: mbox_dsp {

				ti,mbox-tx = <3 0 0>;

				ti,mbox-rx = <0 0 0>;

			};

		};



		mdio: mdio@4a100800 {

			compatible = "ti,davinci_mdio";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x4a100800 0x100>;

			ti,hwmods = "davinci_mdio";

			bus_freq = <1000000>;

			phy0: ethernet-phy@0 {

				reg = <1>;

			};

			phy1: ethernet-phy@1 {

				reg = <2>;

			};

		};



		eth0: ethernet@4a100000 {

			compatible = "ti,dm816-emac";

			ti,hwmods = "emac0";

			reg = <0x4a100000 0x800

			       0x4a100900 0x3700>;

			clocks = <&sysclk24_ck>;

			ti,davinci-ctrl-reg-offset = <0>;

			ti,davinci-ctrl-mod-reg-offset = <0x900>;

			ti,davinci-ctrl-ram-offset = <0x2000>;

			ti,davinci-ctrl-ram-size = <0x2000>;

			interrupts = <40 41 42 43>;

			phy-handle = <&phy0>;

		};



		eth1: ethernet@4a120000 {

			compatible = "ti,dm816-emac";

			ti,hwmods = "emac1";

			reg = <0x4a120000 0x4000>;

			clocks = <&sysclk24_ck>;

			ti,davinci-ctrl-reg-offset = <0>;

			ti,davinci-ctrl-mod-reg-offset = <0x900>;

			ti,davinci-ctrl-ram-offset = <0x2000>;

			ti,davinci-ctrl-ram-size = <0x2000>;

			interrupts = <44 45 46 47>;

			phy-handle = <&phy1>;

		};



		mcspi1: spi@48030000 {

			compatible = "ti,omap4-mcspi";

			reg = <0x48030000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupts = <65>;

			ti,spi-num-cs = <4>;

			ti,hwmods = "mcspi1";

			dmas = <&edma 16 &edma 17

				&edma 18 &edma 19>;

			dma-names = "tx0", "rx0", "tx1", "rx1";

		};



		mmc1: mmc@48060000 {

			compatible = "ti,omap4-hsmmc";

			reg = <0x48060000 0x11000>;

			ti,hwmods = "mmc1";

			interrupts = <64>;

			dmas = <&edma 24 &edma 25>;

			dma-names = "tx", "rx";

		};



		timer1: timer@4802e000 {

			compatible = "ti,dm816-timer";

			reg = <0x4802e000 0x2000>;

			interrupts = <67>;

			ti,hwmods = "timer1";

			ti,timer-alwon;

		};



		timer2: timer@48040000 {

			compatible = "ti,dm816-timer";

			reg = <0x48040000 0x2000>;

			interrupts = <68>;

			ti,hwmods = "timer2";

		};



		timer3: timer@48042000 {

			compatible = "ti,dm816-timer";

			reg = <0x48042000 0x2000>;

			interrupts = <69>;

			ti,hwmods = "timer3";

		};



		timer4: timer@48044000 {

			compatible = "ti,dm816-timer";

			reg = <0x48044000 0x2000>;

			interrupts = <92>;

			ti,hwmods = "timer4";

		};



		timer5: timer@48046000 {

			compatible = "ti,dm816-timer";

			reg = <0x48046000 0x2000>;

			interrupts = <93>;

			ti,hwmods = "timer5";

		};



		timer6: timer@48048000 {

			compatible = "ti,dm816-timer";

			reg = <0x48048000 0x2000>;

			interrupts = <94>;

			ti,hwmods = "timer6";

		};



		timer7: timer@4804a000 {

			compatible = "ti,dm816-timer";

			reg = <0x4804a000 0x2000>;

			interrupts = <95>;

			ti,hwmods = "timer7";

		};



		uart1: uart@48020000 {

			compatible = "ti,omap3-uart";

			ti,hwmods = "uart1";

			reg = <0x48020000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <72>;

			dmas = <&edma 26 &edma 27>;

			dma-names = "tx", "rx";

		};



		uart2: uart@48022000 {

			compatible = "ti,omap3-uart";

			ti,hwmods = "uart2";

			reg = <0x48022000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <73>;

			dmas = <&edma 28 &edma 29>;

			dma-names = "tx", "rx";

		};



		uart3: uart@48024000 {

			compatible = "ti,omap3-uart";

			ti,hwmods = "uart3";

			reg = <0x48024000 0x2000>;

			clock-frequency = <48000000>;

			interrupts = <74>;

			dmas = <&edma 30 &edma 31>;

			dma-names = "tx", "rx";

		};



		/* NOTE: USB needs a transceiver driver for phys to work */

		usb: usb_otg_hs@47401000 {

			compatible = "ti,am33xx-usb";

			reg = <0x47401000 0x400000>;

			ranges;

			#address-cells = <1>;

			#size-cells = <1>;

			ti,hwmods = "usb_otg_hs";



			usb0: usb@47401000 {

				compatible = "ti,musb-am33xx";

				reg = <0x47401400 0x400

				       0x47401000 0x200>;

				reg-names = "mc", "control";

				interrupts = <18>;

				interrupt-names = "mc";

				dr_mode = "otg";

				mentor,multipoint = <1>;

				mentor,num-eps = <16>;

				mentor,ram-bits = <12>;

				mentor,power = <500>;

			};



			usb1: usb@47401800 {

				compatible = "ti,musb-am33xx";

				status = "disabled";

				reg = <0x47401c00 0x400

				       0x47401800 0x200>;

				reg-names = "mc", "control";

				interrupts = <19>;

				interrupt-names = "mc";

				dr_mode = "otg";

				mentor,multipoint = <1>;

				mentor,num-eps = <16>;

				mentor,ram-bits = <12>;

				mentor,power = <500>;

			};

		};



		wd_timer2: wd_timer@480c2000 {

			compatible = "ti,omap3-wdt";

			ti,hwmods = "wd_timer";

			reg = <0x480c2000 0x1000>;

			interrupts = <0>;

		};

	};

};

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