Commit 77f4f622 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'fec-next' 



Florian Fainelli says:

====================
net: phy: Broadcom BCM7xxx PHY workaround update

This patch sets the change to of_phy_connect() that you have seen before,
this time with the full context of why it is useful and applicable here.

Due to some design decision, the internal PHY on Broadcom BCM7xxx chips
is not entirely self contained and does not report its internal revision
through MII_PHYSID2, that is left to external PHY designs.

This forces us to get the PHY revision from the GENET and SF2 switch drivers
because those two peripherals integrate such a PHY and do contain the PHY
revision in their registers.

The approach taken here is hopefully easy to extend to similar needs for
other chips/ as well.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 2e4e4410 d8ebfed3

drivers/net/dsa/bcm_sf2.c

+16 −0
Original line number Diff line number Diff line
@@ -376,6 +376,9 @@ static int bcm_sf2_sw_setup(struct dsa_switch *ds) 
					SWITCH_TOP_REV_MASK;

	priv->hw_params.core_rev = (rev & SF2_REV_MASK);



	rev = reg_readl(priv, REG_PHY_REVISION);

	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;



	pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",

		priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,

		priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
@@ -399,6 +402,18 @@ static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr) 
	return 0;

}



static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);



	/* The BCM7xxx PHY driver expects to find the integrated PHY revision

	 * in bits 15:8 and the patch level in bits 7:0 which is exactly what

	 * the REG_PHY_REVISION register layout is.

	 */



	return priv->hw_params.gphy_rev;

}



static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,

			       int regnum, u16 val)

{
@@ -597,6 +612,7 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = { 
	.probe			= bcm_sf2_sw_probe,

	.setup			= bcm_sf2_sw_setup,

	.set_addr		= bcm_sf2_sw_set_addr,

	.get_phy_flags		= bcm_sf2_sw_get_phy_flags,

	.phy_read		= bcm_sf2_sw_phy_read,

	.phy_write		= bcm_sf2_sw_phy_write,

	.get_strings		= bcm_sf2_sw_get_strings,

drivers/net/dsa/bcm_sf2.h

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
struct bcm_sf2_hw_params {

	u16	top_rev;

	u16	core_rev;

	u16	gphy_rev;

	u32	num_gphy;

	u8	num_acb_queue;

	u8	num_rgmii;

drivers/net/dsa/bcm_sf2_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define  SWITCH_TOP_REV_MASK		0xffff



#define REG_PHY_REVISION		0x1C

#define  PHY_REVISION_MASK		0xffff



#define REG_SPHY_CNTRL			0x2C

#define  IDDQ_BIAS			(1 << 0)

drivers/net/ethernet/broadcom/genet/bcmgenet.c

+7 −0
Original line number Diff line number Diff line
@@ -2432,6 +2432,13 @@ static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 
	dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,

		 major, (reg >> 16) & 0x0f, reg & 0xffff);



	/* Store the integrated PHY revision for the MDIO probing function

	 * to pass this information to the PHY driver. The PHY driver expects

	 * to find the PHY major revision in bits 15:8 while the GENET register

	 * stores that information in bits 7:0, account for that.

	 */

	priv->gphy_rev = (reg & 0xffff) << 8;



#ifdef CONFIG_PHYS_ADDR_T_64BIT

	if (!(params->flags & GENET_HAS_40BITS))

		pr_warn("GENET does not support 40-bits PA\n");

drivers/net/ethernet/broadcom/genet/bcmgenet.h

+1 −0
Original line number Diff line number Diff line
@@ -545,6 +545,7 @@ struct bcmgenet_priv { 
	struct phy_device *phydev;

	struct device_node *phy_dn;

	struct mii_bus *mii_bus;

	u16 gphy_rev;



	/* PHY device variables */

	int old_duplex;

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