Commit 77f255c1 authored by Yunsheng Lin's avatar Yunsheng Lin Committed by David S. Miller
Browse files

net: hns3: Add some interface for the support of DCB feature 



This patch add some interface and export some interface from
hclge_tm and hclgc_main to support the upcoming DCB feature.

Signed-off-by: default avatarYunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent cc9bb43a

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+1 −2
Original line number Diff line number Diff line
@@ -30,7 +30,6 @@ 
#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))

#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))



static int hclge_rss_init_hw(struct hclge_dev *hdev);

static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,

				     enum hclge_mta_dmac_sel_type mta_mac_sel,

				     bool enable);
@@ -2655,7 +2654,7 @@ static int hclge_get_tc_size(struct hnae3_handle *handle) 
	return hdev->rss_size_max;

}



static int hclge_rss_init_hw(struct hclge_dev *hdev)

int hclge_rss_init_hw(struct hclge_dev *hdev)

{

	const  u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;

	struct hclge_vport *vport = hdev->vport;

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h

+3 −0
Original line number Diff line number Diff line
@@ -515,4 +515,7 @@ static inline int hclge_get_queue_id(struct hnae3_queue *queue) 
int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);

int hclge_set_vf_vlan_common(struct hclge_dev *vport, int vfid,

			     bool is_kill, u16 vlan, u8 qos, __be16 proto);



int hclge_buffer_alloc(struct hclge_dev *hdev);

int hclge_rss_init_hw(struct hclge_dev *hdev);

#endif

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c

+45 −3
Original line number Diff line number Diff line
@@ -883,10 +883,14 @@ static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev) 
	return 0;

}



static int hclge_tm_map_cfg(struct hclge_dev *hdev)

int hclge_tm_map_cfg(struct hclge_dev *hdev)

{

	int ret;



	ret = hclge_up_to_tc_map(hdev);

	if (ret)

		return ret;



	ret = hclge_tm_pg_to_pri_map(hdev);

	if (ret)

		return ret;
@@ -994,7 +998,7 @@ static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev) 
	return 0;

}



static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)

int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)

{

	int ret;
@@ -1092,7 +1096,45 @@ int hclge_pause_setup_hw(struct hclge_dev *hdev) 
			return ret;

	}



	return hclge_up_to_tc_map(hdev);

	return 0;

}



int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)

{

	struct hclge_vport *vport = hdev->vport;

	struct hnae3_knic_private_info *kinfo;

	u32 i, k;



	for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {

		if (prio_tc[i] >= hdev->tm_info.num_tc)

			return -EINVAL;

		hdev->tm_info.prio_tc[i] = prio_tc[i];



		for (k = 0;  k < hdev->num_alloc_vport; k++) {

			kinfo = &vport[k].nic.kinfo;

			kinfo->prio_tc[i] = prio_tc[i];

		}

	}

	return 0;

}



void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)

{

	u8 i, bit_map = 0;



	hdev->tm_info.num_tc = num_tc;



	for (i = 0; i < hdev->tm_info.num_tc; i++)

		bit_map |= BIT(i);



	if (!bit_map) {

		bit_map = 1;

		hdev->tm_info.num_tc = 1;

	}



	hdev->hw_tc_map = bit_map;



	hclge_tm_schd_info_init(hdev);

}



int hclge_tm_init_hw(struct hclge_dev *hdev)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h

+6 −0
Original line number Diff line number Diff line
@@ -112,4 +112,10 @@ struct hclge_port_shapping_cmd { 


int hclge_tm_schd_init(struct hclge_dev *hdev);

int hclge_pause_setup_hw(struct hclge_dev *hdev);

int hclge_tm_schd_mode_hw(struct hclge_dev *hdev);

int hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc);

void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc);

int hclge_tm_dwrr_cfg(struct hclge_dev *hdev);

int hclge_tm_map_cfg(struct hclge_dev *hdev);

int hclge_tm_init_hw(struct hclge_dev *hdev);

#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE