Commit 779eb41c authored May 21, 2019 by Benjamin Gaignard Committed by Russell King Jun 21, 2019

ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can execute out of order

The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.

This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.

This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

parent e6c4375f

arch/arm/Kconfig

+12 −0

Original line number	Diff line number	Diff line
		@@ -1250,6 +1250,18 @@ config PCI_HOST_ITE8152
		default y
		select DMABOUNCE

		config ARM_ERRATA_814220
		bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
		depends on CPU_V7
		help
		The v7 ARM states that all cache and branch predictor maintenance
		operations that do not specify an address execute, relative to
		each other, in program order.
		However, because of this erratum, an L2 set/way cache maintenance
		operation can overtake an L1 set/way cache maintenance operation.
		This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
		r0p4, r0p5.

		endmenu

		menu "Kernel Features"

arch/arm/mm/cache-v7.S

+3 −0

Original line number	Diff line number	Diff line
		@@ -171,6 +171,9 @@ loop2:
		skip:
		add r10, r10, #2 @ increment cache number
		cmp r3, r10
		#ifdef CONFIG_ARM_ERRATA_814220
		dsb
		#endif
		bgt flush_levels
		finished:
		mov r10, #0 @ switch back to cache level 0

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