drm/amdgpu: reserve vram for memory training(v4) (778e8c42) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+91 −0

Original line number	Diff line number	Diff line
		@@ -1667,6 +1667,88 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
		&adev->fw_vram_usage.va);
		}

		/*
		* Memoy training reservation functions
		*/

		/**
		* amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
		*
		* @adev: amdgpu_device pointer
		*
		* free memory training reserved vram if it has been reserved.
		*/
		static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
		{
		struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;

		ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
		amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
		ctx->c2p_bo = NULL;

		amdgpu_bo_free_kernel(&ctx->p2c_bo, NULL, NULL);
		ctx->p2c_bo = NULL;

		return 0;
		}

		/**
		* amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
		*
		* @adev: amdgpu_device pointer
		*
		* create bo vram reservation from memory training.
		*/
		static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
		{
		int ret;
		struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;

		memset(ctx, 0, sizeof(*ctx));
		if (!adev->fw_vram_usage.mem_train_support) {
		DRM_DEBUG("memory training does not support!\n");
		return 0;
		}

		ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
		ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
		ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;

		DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
		ctx->train_data_size,
		ctx->p2c_train_data_offset,
		ctx->c2p_train_data_offset);

		ret = amdgpu_bo_create_kernel_at(adev,
		ctx->p2c_train_data_offset,
		ctx->train_data_size,
		AMDGPU_GEM_DOMAIN_VRAM,
		&ctx->p2c_bo,
		NULL);
		if (ret) {
		DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
		goto Err_out;
		}

		ret = amdgpu_bo_create_kernel_at(adev,
		ctx->c2p_train_data_offset,
		ctx->train_data_size,
		AMDGPU_GEM_DOMAIN_VRAM,
		&ctx->c2p_bo,
		NULL);
		if (ret) {
		DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
		goto Err_out;
		}

		ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
		return 0;

		Err_out:
		amdgpu_ttm_training_reserve_vram_fini(adev);
		return ret;
		}

		/**
		* amdgpu_ttm_init - Init the memory management (ttm) as well as various
		* gtt/vram related fields.
		@@ -1740,6 +1822,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
		return r;
		}

		/*
		*The reserved vram for memory training must be pinned to the specified
		*place on the VRAM, so reserve it early.
		*/
		r = amdgpu_ttm_training_reserve_vram_init(adev);
		if (r)
		return r;

		/* allocate memory as required for VGA
		* This is used for VGA emulation and pre-OS scanout buffers to
		* avoid display artifacts while transitioning between pre-OS
		@@ -1842,6 +1932,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
		return;

		amdgpu_ttm_debugfs_fini(adev);
		amdgpu_ttm_training_reserve_vram_fini(adev);
		amdgpu_ttm_fw_reserve_vram_fini(adev);
		if (adev->mman.aper_base_kaddr)
		iounmap(adev->mman.aper_base_kaddr);

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