Commit 77899dd2 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core 



Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
ARM Generic Interrupt Controller and Architectured Timer.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent aa7a6365

arch/arm64/boot/dts/renesas/r8a77970.dtsi

+15 −5
Original line number Diff line number Diff line
@@ -41,6 +41,16 @@ 
			enable-method = "psci";

		};



		a53_1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <1>;

			clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;

			power-domains = <&sysc R8A77970_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		L2_CA53: cache-controller {

			compatible = "cache";

			power-domains = <&sysc R8A77970_PD_CA53_SCU>;
@@ -635,7 +645,7 @@ 
			      <0 0xf1020000 0 0x20000>,

			      <0 0xf1040000 0 0x20000>,

			      <0 0xf1060000 0 0x20000>;

			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |

			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(2) |

				      IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";
@@ -726,9 +736,9 @@ 


	timer {

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;

	};

};

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