drm/tegra: dc: Use atomic clock state in modeset

	return 0;

}

static void tegra_dc_commit_state(struct tegra_dc *dc,

				  struct tegra_dc_state *state)

{

	u32 value;

	int err;

	err = clk_set_parent(dc->clk, state->clk);

	if (err < 0)

		dev_err(dc->dev, "failed to set parent clock: %d\n", err);

	/*

	 * Outputs may not want to change the parent clock rate. This is only

	 * relevant to Tegra20 where only a single display PLL is available.

	 * Since that PLL would typically be used for HDMI, an internal LVDS

	 * panel would need to be driven by some other clock such as PLL_P

	 * which is shared with other peripherals. Changing the clock rate

	 * should therefore be avoided.

	 */

	if (state->pclk > 0) {

		err = clk_set_rate(state->clk, state->pclk);

		if (err < 0)

			dev_err(dc->dev,

				"failed to set clock rate to %lu Hz\n",

				state->pclk);

	}

	DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),

		      state->div);

	DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);

	value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;

	tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);

}

static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)

{

	struct drm_display_mode *mode = &crtc->state->adjusted_mode;

	struct tegra_dc_state *state = to_dc_state(crtc->state);

	struct tegra_dc *dc = to_tegra_dc(crtc);

	u32 value;

	tegra_dc_commit_state(dc, state);

	/* program display mode */

	tegra_dc_set_timings(dc, mode);