iommu/mediatek: Fix iova_to_phys PA start for 4GB mode (76ce6546) · Commits · 戴 / test

In M4U 4GB mode, the physical address is remapped as below: CPU Physical address: ==================== 0 1G 2G 3G 4G 5G |---A---|---B---|---C---|---D---|---E---| +--I/O--+------------Memory-------------+ IOMMU output physical address: ============================= 4G 5G 6G 7G 8G |---E---|---B---|---C---|---D---| +------------Memory-------------+ The Region 'A'(I/O) can not be mapped by M4U; For Region 'B'/'C'/'D', the bit32 of the CPU physical address always is needed to set, and for Region 'E', the CPU physical address keep as is. something looks like this: CPU PA -> M4U OUTPUT PA 0x4000_0000 0x1_4000_0000 (Add bit32) 0x8000_0000 0x1_8000_0000 ... 0xc000_0000 0x1_c000_0000 ... 0x1_0000_0000 0x1_0000_0000 (No change) Additionally, the iommu consumers always use the CPU phyiscal address. The PA in the iova_to_phys that is got from v7s always is u32, But from the CPU point of view, PA only need add BIT(32) when PA < 0x4000_0000. Fixes: ("iommu/mediatek: Enlarge the validate PA range for 4GB mode") Signed-off-by:

Yong Wu <yong.wu@mediatek.com> Signed-off-by:

Joerg Roedel <jroedel@suse.de>

drivers/iommu/mtk_iommu.c

+25 −1

Original line number	Diff line number	Diff line
		@@ -107,6 +107,30 @@ struct mtk_iommu_domain {

		static const struct iommu_ops mtk_iommu_ops;

		/*
		* In M4U 4GB mode, the physical address is remapped as below:
		*
		* CPU Physical address:
		* ====================
		*
		* 0 1G 2G 3G 4G 5G
		* \|---A---\|---B---\|---C---\|---D---\|---E---\|
		* +--I/O--+------------Memory-------------+
		*
		* IOMMU output physical address:
		* =============================
		*
		* 4G 5G 6G 7G 8G
		* \|---E---\|---B---\|---C---\|---D---\|
		* +------------Memory-------------+
		*
		* The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
		* bit32 of the CPU physical address always is needed to set, and for Region
		* 'E', the CPU physical address keep as is.
		* Additionally, The iommu consumers always use the CPU phyiscal address.
		*/
		#define MTK_IOMMU_4GB_MODE_REMAP_BASE 0x40000000

		static LIST_HEAD(m4ulist); /* List all the M4U HWs */

		#define for_each_m4u(data) list_for_each_entry(data, &m4ulist, list)
		@@ -401,7 +425,7 @@ static phys_addr_t mtk_iommu_iova_to_phys(struct iommu_domain *domain,
		pa = dom->iop->iova_to_phys(dom->iop, iova);
		spin_unlock_irqrestore(&dom->pgtlock, flags);

		if (data->enable_4GB)
		if (data->enable_4GB && pa < MTK_IOMMU_4GB_MODE_REMAP_BASE)
		pa \|= BIT_ULL(32);

		return pa;

Admin message