drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting (76c71f00) · Commits · 戴 / test

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -575,6 +575,7 @@ struct pptable_funcs {
		int (get_fan_parameters)(struct smu_context smu);
		int (post_init)(struct smu_context smu);
		void (interrupt_work)(struct smu_context smu);
		int (gpo_control)(struct smu_context smu, bool enablement);
		};

		typedef enum {

+1 −0

Original line number	Diff line number	Diff line
		@@ -184,6 +184,7 @@
		__SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
		__SMU_DUMMY_MAP(PowerUpCvip), \
		__SMU_DUMMY_MAP(PowerDownCvip), \
		__SMU_DUMMY_MAP(SetGpoFeaturePMask), \

		#undef __SMU_DUMMY_MAP
		#define __SMU_DUMMY_MAP(type) SMU_MSG_##type

+2 −0

Original line number	Diff line number	Diff line
		@@ -1406,6 +1406,7 @@ static int smu_enable_umd_pstate(void *handle,
		if (*level & profile_mode_mask) {
		smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
		smu_dpm_ctx->enable_umd_pstate = true;
		smu_gpo_control(smu, false);
		amdgpu_device_ip_set_powergating_state(smu->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_PG_STATE_UNGATE);
		@@ -1431,6 +1432,7 @@ static int smu_enable_umd_pstate(void *handle,
		amdgpu_device_ip_set_powergating_state(smu->adev,
		AMD_IP_BLOCK_TYPE_GFX,
		AMD_PG_STATE_GATE);
		smu_gpo_control(smu, true);
		}
		}

+22 −0

Original line number	Diff line number	Diff line
		@@ -127,6 +127,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
		MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
		MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
		MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
		MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
		};

		static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
		@@ -2714,6 +2715,26 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
		NULL);
		}

		static int sienna_cichlid_gpo_control(struct smu_context *smu,
		bool enablement)
		{
		int ret = 0;

		if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
		if (enablement)
		ret = smu_cmn_send_smc_msg_with_param(smu,
		SMU_MSG_SetGpoFeaturePMask,
		GFX_GPO_PACE_MASK \| GFX_GPO_DEM_MASK,
		NULL);
		else
		ret = smu_cmn_send_smc_msg_with_param(smu,
		SMU_MSG_SetGpoFeaturePMask,
		0,
		NULL);
		}

		return ret;
		}
		static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
		.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
		.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
		@@ -2795,6 +2816,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
		.deep_sleep_control = smu_v11_0_deep_sleep_control,
		.get_fan_parameters = sienna_cichlid_get_fan_parameters,
		.interrupt_work = smu_v11_0_interrupt_work,
		.gpo_control = sienna_cichlid_gpo_control,
		};

		void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)

+1 −0

Original line number	Diff line number	Diff line
		@@ -89,6 +89,7 @@
		#define smu_deep_sleep_control(smu, enablement) smu_ppt_funcs(deep_sleep_control, 0, smu, enablement)
		#define smu_get_fan_parameters(smu) smu_ppt_funcs(get_fan_parameters, 0, smu)
		#define smu_post_init(smu) smu_ppt_funcs(post_init, 0, smu)
		#define smu_gpo_control(smu, enablement) smu_ppt_funcs(gpo_control, 0, smu, enablement)

		#endif
		#endif