memory: tegra: Fix missed registers values latching (76b959a4) · Commits · 戴 / test

Some of Memory Controller registers are shadowed and require latching in order to copy assembly state into the active, MC_EMEM_ARB_CFG is one of these registers. Signed-off-by:

Dmitry Osipenko <digetx@gmail.com> Signed-off-by:

Thierry Reding <treding@nvidia.com>

drivers/memory/tegra/mc.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,9 @@
		#define MC_EMEM_ADR_CFG 0x54
		#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)

		#define MC_TIMING_CONTROL 0xfc
		#define MC_TIMING_UPDATE BIT(0)

		static const struct of_device_id tegra_mc_of_match[] = {
		#ifdef CONFIG_ARCH_TEGRA_2x_SOC
		{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
		@@ -301,6 +304,9 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
		writel(value, mc->regs + la->reg);
		}

		/* latch new values */
		writel(MC_TIMING_UPDATE, mc->regs + MC_TIMING_CONTROL);

		return 0;
		}

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