Commit 767bf9f0 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v3.15/fixes-v3-signed' of... 

Merge tag 'omap-for-v3.15/fixes-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Pull "omap fixes for v3.15-rc cycle" from Tony Lindgren:

Regression fixes for omaps for NAND, DMA, cpu_idle and audio.
Also a minor one line fix for audio clock on 54xx.

* tag 'omap-for-v3.15/fixes-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: OMAP4: Fix the boot regression with CPU_IDLE enabled
  ARM: OMAP2+: Fix DMA hang after off-idle
  ARM: OMAP2+: nand: Fix NAND on OMAP2 and OMAP3 boards
  ARM: omap5: hwmod_data: Correct IDLEMODE for McPDM
  ARM: OMAP3: clock: Back-propagate rate change from cam_mclk to dpll4_m5 on all OMAP3 platforms

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents d1d70e5d 4b353a70

arch/arm/mach-omap2/board-flash.c

+1 −1
Original line number Diff line number Diff line
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, 
	board_nand_data.nr_parts	= nr_parts;

	board_nand_data.devsize		= nand_type;



	board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;

	board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;

	gpmc_nand_init(&board_nand_data, gpmc_t);

}

#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */

arch/arm/mach-omap2/cclock3xxx_data.c

+2 −1
Original line number Diff line number Diff line
@@ -456,7 +456,8 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = { 
	.clkdm_name	= "dpll4_clkdm",

};



DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);

DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,

			dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);



static struct clk dpll4_m5x2_ck_3630 = {

	.name		= "dpll4_m5x2_ck",

arch/arm/mach-omap2/cpuidle44xx.c

+21 −4
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/cpuidle.h>

#include <linux/cpu_pm.h>

#include <linux/export.h>

#include <linux/clockchips.h>



#include <asm/cpuidle.h>

#include <asm/proc-fns.h>
@@ -83,6 +84,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, 
{

	struct idle_statedata *cx = state_ptr + index;

	u32 mpuss_can_lose_context = 0;

	int cpu_id = smp_processor_id();



	/*

	 * CPU0 has to wait and stay ON until CPU1 is OFF state.
@@ -110,6 +112,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, 
	mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&

				 (cx->mpu_logic_state == PWRDM_POWER_OFF);



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);



	/*

	 * Call idle CPU PM enter notifier chain so that

	 * VFP and per CPU interrupt context is saved.
@@ -165,6 +169,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, 
	if (dev->cpu == 0 && mpuss_can_lose_context)

		cpu_cluster_pm_exit();



	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);



fail:

	cpuidle_coupled_parallel_barrier(dev, &abort_barrier);

	cpu_done[dev->cpu] = false;
@@ -172,6 +178,16 @@ fail: 
	return index;

}



/*

 * For each cpu, setup the broadcast timer because local timers

 * stops for the states above C1.

 */

static void omap_setup_broadcast_timer(void *arg)

{

	int cpu = smp_processor_id();

	clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);

}



static struct cpuidle_driver omap4_idle_driver = {

	.name				= "omap4_idle",

	.owner				= THIS_MODULE,
@@ -189,8 +205,7 @@ static struct cpuidle_driver omap4_idle_driver = { 
			/* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */

			.exit_latency = 328 + 440,

			.target_residency = 960,

			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |

			         CPUIDLE_FLAG_TIMER_STOP,

			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,

			.enter = omap_enter_idle_coupled,

			.name = "C2",

			.desc = "CPUx OFF, MPUSS CSWR",
@@ -199,8 +214,7 @@ static struct cpuidle_driver omap4_idle_driver = { 
			/* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */

			.exit_latency = 460 + 518,

			.target_residency = 1100,

			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |

			         CPUIDLE_FLAG_TIMER_STOP,

			.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,

			.enter = omap_enter_idle_coupled,

			.name = "C3",

			.desc = "CPUx OFF, MPUSS OSWR",
@@ -231,5 +245,8 @@ int __init omap4_idle_init(void) 
	if (!cpu_clkdm[0] || !cpu_clkdm[1])

		return -ENODEV;



	/* Configure the broadcast timer on each cpu */

	on_each_cpu(omap_setup_broadcast_timer, NULL, 1);



	return cpuidle_register(&omap4_idle_driver, cpu_online_mask);

}

arch/arm/mach-omap2/omap_hwmod_54xx_data.c

+1 −1
Original line number Diff line number Diff line
@@ -895,7 +895,7 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = { 
	 * current exception.

	 */



	.flags		= HWMOD_EXT_OPT_MAIN_CLK,

	.flags		= HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,

	.main_clk	= "pad_clks_ck",

	.prcm = {

		.omap4 = {

arch/arm/plat-omap/dma.c

+10 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ static u32 errata; 


static struct omap_dma_global_context_registers {

	u32 dma_irqenable_l0;

	u32 dma_irqenable_l1;

	u32 dma_ocp_sysconfig;

	u32 dma_gcr;

} omap_dma_global_context;
@@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq; 


/*----------------------------------------------------------------------------*/



/*

 * Note that we are currently using only IRQENABLE_L0 and L1.

 * As the DSP may be using IRQENABLE_L2 and L3, let's not

 * touch those for now.

 */

void omap_dma_global_context_save(void)

{

	omap_dma_global_context.dma_irqenable_l0 =

		p->dma_read(IRQENABLE_L0, 0);

	omap_dma_global_context.dma_irqenable_l1 =

		p->dma_read(IRQENABLE_L1, 0);

	omap_dma_global_context.dma_ocp_sysconfig =

		p->dma_read(OCP_SYSCONFIG, 0);

	omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
@@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void) 
		OCP_SYSCONFIG, 0);

	p->dma_write(omap_dma_global_context.dma_irqenable_l0,

		IRQENABLE_L0, 0);

	p->dma_write(omap_dma_global_context.dma_irqenable_l1,

		IRQENABLE_L1, 0);



	if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))

		p->dma_write(0x3 , IRQSTATUS_L0, 0);

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