Commit 767acabd authored by Kevin Wang's avatar Kevin Wang Committed by Alex Deucher
Browse files

drm/amd/powerplay: add baco smu reset function for smu11 



add baco reset support for smu11.
it can help gpu do asic reset when gpu recovery.

Signed-off-by: default avatarKevin Wang <kevin1.wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e3000669

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+3 −2
Original line number Diff line number Diff line
@@ -245,8 +245,9 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, 
	mutex_lock(&adev->mman.gtt_window_lock);



	gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0);

	if (!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||

	    adev->asic_type != CHIP_NAVI10) {

	if (!adev->mman.buffer_funcs_enabled ||

	    !adev->ib_pool_ready ||

	    adev->in_gpu_reset) {

		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0);

		mutex_unlock(&adev->mman.gtt_window_lock);

		return;

drivers/gpu/drm/amd/amdgpu/nv.c

+8 −1
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "amdgpu_vce.h"

#include "amdgpu_ucode.h"

#include "amdgpu_psp.h"

#include "amdgpu_smu.h"

#include "atom.h"

#include "amd_pcie.h"
@@ -266,8 +267,14 @@ static int nv_asic_reset(struct amdgpu_device *adev) 


	amdgpu_atombios_scratch_regs_engine_hung(adev, false);

#endif

	int ret = 0;

	struct smu_context *smu = &adev->smu;



	return 0;

	if (smu_baco_is_support(smu)) {

		ret = smu_baco_reset(smu);

	}



	return ret;

}



static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+14 −0
Original line number Diff line number Diff line
@@ -634,6 +634,11 @@ static int smu_sw_init(void *handle) 
	bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);

	bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);

	bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);



	mutex_init(&smu->smu_baco.mutex);

	smu->smu_baco.state = SMU_BACO_STATE_EXIT;

	smu->smu_baco.platform_support = false;



	smu->watermarks_bitmap = 0;

	smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;

	smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
@@ -1103,11 +1108,20 @@ static int smu_suspend(void *handle) 
	int ret;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct smu_context *smu = &adev->smu;

	bool baco_feature_is_enabled = smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT);



	ret = smu_system_features_control(smu, false);

	if (ret)

		return ret;



	if (adev->in_gpu_reset && baco_feature_is_enabled) {

		ret = smu_feature_set_enabled(smu, SMU_FEATURE_BACO_BIT, true);

		if (ret) {

			pr_warn("set BACO feature enabled failed, return %d\n", ret);

			return ret;

		}

	}



	smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);



	if (adev->asic_type >= CHIP_NAVI10 &&

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+26 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ enum smu_message_type 
	SMU_MSG_PowerUpJpeg,

	SMU_MSG_PowerDownJpeg,

	SMU_MSG_BacoAudioD3PME,

	SMU_MSG_ArmD3,

	SMU_MSG_MAX_COUNT,

};
@@ -489,6 +490,19 @@ struct mclock_latency_table { 
	struct mclk_latency_entries  entries[MAX_REGULAR_DPM_NUM];

};



enum smu_baco_state

{

	SMU_BACO_STATE_ENTER = 0,

	SMU_BACO_STATE_EXIT,

};



struct smu_baco_context

{

	struct mutex mutex;

	uint32_t state;

	bool platform_support;

};



#define WORKLOAD_POLICY_MAX 7

struct smu_context

{
@@ -505,6 +519,7 @@ struct smu_context 
	struct smu_power_context	smu_power;

	struct smu_feature		smu_feature;

	struct amd_pp_display_configuration  *display_config;

	struct smu_baco_context		smu_baco;

	void *od_settings;



	uint32_t pstate_sclk;
@@ -680,6 +695,11 @@ struct smu_funcs 
	int (*register_irq_handler)(struct smu_context *smu);

	int (*set_azalia_d3_pme)(struct smu_context *smu);

	int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);

	bool (*baco_is_support)(struct smu_context *smu);

	enum smu_baco_state (*baco_get_state)(struct smu_context *smu);

	int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);

	int (*baco_reset)(struct smu_context *smu);



};



#define smu_init_microcode(smu) \
@@ -892,6 +912,12 @@ struct smu_funcs 
	((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)

#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \

	((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)

#define smu_baco_is_support(smu) \

	((smu)->funcs->baco_is_support? (smu)->funcs->baco_is_support((smu)) : false)

#define smu_baco_get_state(smu, state) \

	((smu)->funcs->baco_get_state? (smu)->funcs->baco_get_state((smu), (state)) : 0)

#define smu_baco_reset(smu) \

	((smu)->funcs->baco_reset? (smu)->funcs->baco_reset((smu)) : 0)



extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,

				   uint16_t *size, uint8_t *frev, uint8_t *crev,

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+8 −0
Original line number Diff line number Diff line
@@ -105,6 +105,14 @@ struct smu_11_0_power_context { 
	enum smu_11_0_power_state power_state;

};



enum smu_v11_0_baco_seq {

	BACO_SEQ_BACO = 0,

	BACO_SEQ_MSR,

	BACO_SEQ_BAMACO,

	BACO_SEQ_ULPS,

	BACO_SEQ_COUNT,

};



void smu_v11_0_set_smu_funcs(struct smu_context *smu);



#endif

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