clk: meson: gxbb: fix wrong clock for SARADC/SANA (75eccf5e) · Commits · 戴 / test

According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl-s905x-p212 board. The following published datasheets are wrong and should be updated [1] GXBB v1.1.4 [2] GXL v0.3_20170314 Fixes: ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by:

Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by:

Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:

Jerome Brunet <jbrunet@baylibre.com>

drivers/clk/meson/gxbb.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1386,7 +1386,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
		static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
		static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
		static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
		static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
		static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
		static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
		static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
		static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
		@@ -1437,7 +1437,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
		static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
		static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
		static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
		static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
		static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
		static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
		static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
		static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);

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