Commit 75acebf2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "Various fixes.

  The -g perf report lockup you reported is only partially addressed,
  patches that fix the excessive runtime are still being worked on"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86: Fix uncore PCI fixed counter handling
  uprobes: Fix utask->depth accounting in handle_trampoline()
  perf/x86: Add constraint for IVB CYCLE_ACTIVITY:CYCLES_LDM_PENDING
  perf: Fix up MMAP2 buffer space reservation
  perf tools: Add attr->mmap2 support
  perf kvm: Fix sample_type manipulation
  perf evlist: Fix id pos in perf_evlist__open()
  perf trace: Handle perf.data files with no tracepoints
  perf session: Separate progress bar update when processing events
  perf trace: Check if MAP_32BIT is defined
  perf hists: Fix formatting of long symbol names
  perf evlist: Fix parsing with no sample_id_all bit set
  perf tools: Add test for parsing with no sample_id_all bit
  perf trace: Check control+C more often
parents b55ee281 dbc33f70

arch/x86/kernel/cpu/perf_event_intel.c

+1 −0
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ static struct event_constraint intel_ivb_event_constraints[] __read_mostly = 
	INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */

	INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */

	INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */

	INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */

	INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */

	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */

	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */

arch/x86/kernel/cpu/perf_event_intel_uncore.c

+4 −2
Original line number Diff line number Diff line
@@ -2808,7 +2808,7 @@ uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *eve 
			return c;

	}



	if (event->hw.config == ~0ULL)

	if (event->attr.config == UNCORE_FIXED_EVENT)

		return &constraint_fixed;



	if (type->constraints) {
@@ -3112,7 +3112,9 @@ static int uncore_pmu_event_init(struct perf_event *event) 
		 */

		if (pmu->type->single_fixed && pmu->pmu_idx > 0)

			return -EINVAL;

		hwc->config = ~0ULL;



		/* fixed counters have event field hardcoded to zero */

		hwc->config = 0ULL;

	} else {

		hwc->config = event->attr.config & pmu->type->event_mask;

		if (pmu->type->ops->hw_config) {

kernel/events/core.c

+1 −0
Original line number Diff line number Diff line
@@ -5039,6 +5039,7 @@ static void perf_event_mmap_output(struct perf_event *event, 
		mmap_event->event_id.header.size += sizeof(mmap_event->maj);

		mmap_event->event_id.header.size += sizeof(mmap_event->min);

		mmap_event->event_id.header.size += sizeof(mmap_event->ino);

		mmap_event->event_id.header.size += sizeof(mmap_event->ino_generation);

	}



	perf_event_header__init_id(&mmap_event->event_id.header, &sample, event);

kernel/events/uprobes.c

+1 −3
Original line number Diff line number Diff line
@@ -1682,12 +1682,10 @@ static bool handle_trampoline(struct pt_regs *regs) 
		tmp = ri;

		ri = ri->next;

		kfree(tmp);

		utask->depth--;



		if (!chained)

			break;



		utask->depth--;



		BUG_ON(!ri);

	}

tools/perf/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -394,6 +394,8 @@ ifeq ($(ARCH),x86) 
LIB_OBJS += $(OUTPUT)tests/perf-time-to-tsc.o

endif

LIB_OBJS += $(OUTPUT)tests/code-reading.o

LIB_OBJS += $(OUTPUT)tests/sample-parsing.o

LIB_OBJS += $(OUTPUT)tests/parse-no-sample-id-all.o



BUILTIN_OBJS += $(OUTPUT)builtin-annotate.o

BUILTIN_OBJS += $(OUTPUT)builtin-bench.o
@@ -439,7 +441,6 @@ PERFLIBS = $(LIB_FILE) $(LIBLK) $(LIBTRACEEVENT) 
ifneq ($(OUTPUT),)

  CFLAGS += -I$(OUTPUT)

endif

LIB_OBJS += $(OUTPUT)tests/sample-parsing.o



ifdef NO_LIBELF

EXTLIBS := $(filter-out -lelf,$(EXTLIBS))

CRA Git | Maintained and supported by SUSTech CRA and CCSE