Commit 75a4a04e authored by Sylwester Nawrocki's avatar Sylwester Nawrocki Committed by Krzysztof Kozlowski
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ARM: dts: samsung: odroid-xu3: Move assigned-clock* properties to i2s0 node 



The purpose of those assigned-clock-* properties is to configure clock for
for the I2S device so move them to respective node.

This suppresses the dtbs_check warning:
  arch/arm/boot/dts/exynos5422-odroidxu3.dt.yaml: sound: 'clocks' is a dependency of 'assigned-clocks'

Reported-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent cd5b0321

arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi

+27 −33
Original line number Diff line number Diff line
@@ -29,30 +29,6 @@ 
			"HiFi Playback", "Mixer DAI TX",

			"Mixer DAI RX", "HiFi Capture";



		assigned-clocks = <&clock CLK_MOUT_EPLL>,

				<&clock CLK_MOUT_MAU_EPLL>,

				<&clock CLK_MOUT_USER_MAU_EPLL>,

				<&clock_audss EXYNOS_MOUT_AUDSS>,

				<&clock_audss EXYNOS_MOUT_I2S>,

				<&clock_audss EXYNOS_DOUT_SRP>,

				<&clock_audss EXYNOS_DOUT_AUD_BUS>,

				<&clock_audss EXYNOS_DOUT_I2S>;



		assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

				<&clock CLK_MOUT_EPLL>,

				<&clock CLK_MOUT_MAU_EPLL>,

				<&clock CLK_MAU_EPLL>,

				<&clock_audss EXYNOS_MOUT_AUDSS>;



		assigned-clock-rates = <0>,

				<0>,

				<0>,

				<0>,

				<0>,

				<196608001>,

				<(196608002 / 2)>,

				<196608000>;



		cpu {

			sound-dai = <&i2s0 0>, <&i2s0 1>;

		};
@@ -62,13 +38,6 @@ 
	};

};



&clock_audss {

	assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,

			  <&clock CLK_FOUT_EPLL>;

	assigned-clock-rates = <(196608000 / 256)>,

			       <196608000>;

};



&hsi2c_5 {

	status = "okay";

	max98090: max98090@10 {
@@ -84,6 +53,31 @@ 


&i2s0 {

	status = "okay";

	assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;

	assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;

	assigned-clocks = <&clock CLK_MOUT_EPLL>,

			<&clock CLK_MOUT_MAU_EPLL>,

			<&clock CLK_MOUT_USER_MAU_EPLL>,

			<&clock_audss EXYNOS_MOUT_AUDSS>,

			<&clock_audss EXYNOS_MOUT_I2S>,

			<&i2s0 CLK_I2S_RCLK_SRC>,

			<&clock_audss EXYNOS_DOUT_SRP>,

			<&clock_audss EXYNOS_DOUT_AUD_BUS>,

			<&clock_audss EXYNOS_DOUT_I2S>;



	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,

			<&clock CLK_MOUT_EPLL>,

			<&clock CLK_MOUT_MAU_EPLL>,

			<&clock CLK_MAU_EPLL>,

			<&clock_audss EXYNOS_MOUT_AUDSS>,

			<&clock_audss EXYNOS_SCLK_I2S>;



	assigned-clock-rates = <0>,

			<0>,

			<0>,

			<0>,

			<0>,

			<0>,

			<196608001>,

			<(196608002 / 2)>,

			<196608000>;



};

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