Commit 7596ab68 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10 



To differentiate the mtypes across asics.

Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c304b9e5

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+2 −2
Original line number Diff line number Diff line
@@ -962,8 +962,8 @@ int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 
			goto gart_bind_fail;



		/* Patch mtype of the second part BO */

		flags &=  ~AMDGPU_PTE_MTYPE_MASK;

		flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);

		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;

		flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);



		r = amdgpu_gart_bind(adev,

				gtt->offset + (page_idx << PAGE_SHIFT),

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+2 −2
Original line number Diff line number Diff line
@@ -1578,8 +1578,8 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev, 
		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;

		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);

	} else {

		flags &= ~AMDGPU_PTE_MTYPE_MASK;

		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);

		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;

		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK);

	}



	if ((mapping->flags & AMDGPU_PTE_PRT) &&

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+3 −3
Original line number Diff line number Diff line
@@ -75,8 +75,8 @@ struct amdgpu_bo_list_entry; 




/* For GFX9 */

#define AMDGPU_PTE_MTYPE(a)	((uint64_t)(a) << 57)

#define AMDGPU_PTE_MTYPE_MASK	AMDGPU_PTE_MTYPE(3ULL)

#define AMDGPU_PTE_MTYPE_VG10(a)	((uint64_t)(a) << 57)

#define AMDGPU_PTE_MTYPE_VG10_MASK	AMDGPU_PTE_MTYPE_VG10(3ULL)



#define AMDGPU_MTYPE_NC 0

#define AMDGPU_MTYPE_CC 2
@@ -86,7 +86,7 @@ struct amdgpu_bo_list_entry; 
                                | AMDGPU_PTE_EXECUTABLE \

                                | AMDGPU_PTE_READABLE   \

                                | AMDGPU_PTE_WRITEABLE  \

                                | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC))

                                | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))



/* NAVI10 only */

#define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+7 −7
Original line number Diff line number Diff line
@@ -531,22 +531,22 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev, 


	switch (flags & AMDGPU_VM_MTYPE_MASK) {

	case AMDGPU_VM_MTYPE_DEFAULT:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);

		break;

	case AMDGPU_VM_MTYPE_NC:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);

		break;

	case AMDGPU_VM_MTYPE_WC:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_WC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);

		break;

	case AMDGPU_VM_MTYPE_CC:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_CC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);

		break;

	case AMDGPU_VM_MTYPE_UC:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_UC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);

		break;

	default:

		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);

		pte_flag |= AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);

		break;

	}
@@ -913,7 +913,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev) 
	if (r)

		return r;

	adev->gart.table_size = adev->gart.num_gpu_pages * 8;

	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) |

	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |

				 AMDGPU_PTE_EXECUTABLE;

	return amdgpu_gart_table_vram_alloc(adev);

}

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