Commit 75704ecf authored Dec 04, 2013 by Nicolin Chen Committed by Mark Brown Dec 05, 2013

ASoC: wm8962: Enable SYSCLK provisonally before fetching generated DSPCLK_DIV

DSPCLK_DIV can be only generated correctly after enabling SYSCLK. But if the
current bias_level hasn't reached SND_SOC_BIAS_ON, DAPM won't enable SYSCLK,
which would cause the calculation result from DSPCLK_DIV invalid since bit
DSPCLK_DIV will be finally turned to its true value after DAPM enables SYSCLK
while the driver won't calculate it again for the current instance. In this
circumstance, a playback which needs non-zero DSPCLK_DIV would be distorted
due to unexpected clock frequency resulted from an invalid DSPCLK_DIV value.

So this patch provisionally enables the SYSCLK to get a valid DSPCLK_DIV for
calculation and then disables it afterward.

Signed-off-by: Nicolin Chen <b42378@freescale.com>
Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>

parent 6ce4eac1

sound/soc/codecs/wm8962.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -2439,7 +2439,20 @@ static void wm8962_configure_bclk(struct snd_soc_codec *codec)
		snd_soc_update_bits(codec, WM8962_CLOCKING_4,
		WM8962_SYSCLK_RATE_MASK, clocking4);

		/* DSPCLK_DIV can be only generated correctly after enabling SYSCLK.
		* So we here provisionally enable it and then disable it afterward
		* if current bias_level hasn't reached SND_SOC_BIAS_ON.
		*/
		if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
		snd_soc_update_bits(codec, WM8962_CLOCKING2,
		WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA);

		dspclk = snd_soc_read(codec, WM8962_CLOCKING1);

		if (codec->dapm.bias_level != SND_SOC_BIAS_ON)
		snd_soc_update_bits(codec, WM8962_CLOCKING2,
		WM8962_SYSCLK_ENA_MASK, 0);

		if (dspclk < 0) {
		dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
		return;

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