Merge branch 'spi-5.6' into spi-next

 - clock-names: Should be "clk_apb5".

 - pinctrl-names : a pinctrl state named "default" must be defined.

 - pinctrl-0 : phandle referencing pin configuration of the device.

 - resets : phandle to the reset control for this device.

 - cs-gpios: Specifies the gpio pins to be used for chipselects.

            See: Documentation/devicetree/bindings/spi/spi-bus.txt

- clock-frequency : Input clock frequency to the PSPI block in Hz.

		    Default is 25000000 Hz.

Aliases:

- All the SPI controller nodes should be represented in the aliases node using

  the following format 'spi{n}' withe the correct numbered in "aliases" node.

Example:

aliases {

	spi0 = &spi0;

};

spi0: spi@f0200000 {

	compatible = "nuvoton,npcm750-pspi";

	reg = <0xf0200000 0x1000>;

	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&clk NPCM7XX_CLK_APB5>;

	clock-names = "clk_apb5";

	resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>

	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;

};

STMicroelectronics STM32 SPI Controller

The STM32 SPI controller is used to communicate with external devices using

the Serial Peripheral Interface. It supports full-duplex, half-duplex and

simplex synchronous serial communication with external devices. It supports

from 4 to 32-bit data size. Although it can be configured as master or slave,

only master is supported by the driver.

Required properties:

- compatible: Should be one of:

  "st,stm32h7-spi"

  "st,stm32f4-spi"

- reg: Offset and length of the device's register set.

- interrupts: Must contain the interrupt id.

- clocks: Must contain an entry for spiclk (which feeds the internal clock

	  generator).

- #address-cells:  Number of cells required to define a chip select address.

- #size-cells: Should be zero.

Optional properties:

- resets: Must contain the phandle to the reset controller.

- A pinctrl state named "default" may be defined to set pins in mode of

  operation for SPI transfer.

- dmas: DMA specifiers for tx and rx dma. DMA fifo mode must be used. See the

  STM32 DMA bindings, Documentation/devicetree/bindings/dma/stm32-dma.txt.

- dma-names: DMA request names should include "tx" and "rx" if present.

- cs-gpios: list of GPIO chip selects. See the SPI bus bindings,

  Documentation/devicetree/bindings/spi/spi-bus.txt

Child nodes represent devices on the SPI bus

  See ../spi/spi-bus.txt

Optional properties:

- st,spi-midi-ns: Only for STM32H7, (Master Inter-Data Idleness) minimum time

		  delay in nanoseconds inserted between two consecutive data

		  frames.

Example:

	spi2: spi@40003800 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "st,stm32h7-spi";

		reg = <0x40003800 0x400>;

		interrupts = <36>;

		clocks = <&rcc SPI2_CK>;

		resets = <&rcc 1166>;

		dmas = <&dmamux1 0 39 0x400 0x01>,

		       <&dmamux1 1 40 0x400 0x01>;

		dma-names = "rx", "tx";

		pinctrl-0 = <&spi2_pins_b>;

		pinctrl-names = "default";

		cs-gpios = <&gpioa 11 0>;

		aardvark@0 {

			compatible = "totalphase,aardvark";

			reg = <0>;

			spi-max-frequency = <4000000>;

			st,spi-midi-ns = <4000>;

		};

	};

Atmel SPI device

Required properties:

- compatible : should be "atmel,at91rm9200-spi".

- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".

- reg: Address and length of the register set for the device

- interrupts: Should contain spi interrupt

- cs-gpios: chipselects (optional for SPI controller version >= 2 with the

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 SPI Controller bindings

description: |

  The STM32 SPI controller is used to communicate with external devices using

  the Serial Peripheral Interface. It supports full-duplex, half-duplex and

  simplex synchronous serial communication with external devices. It supports

  from 4 to 32-bit data size.

maintainers:

  - Erwan Leray <erwan.leray@st.com>

  - Fabrice Gasnier <fabrice.gasnier@st.com>

allOf:

  - $ref: "spi-controller.yaml#"

  - if:

      properties:

        compatible:

          contains:

            const: st,stm32f4-spi

    then:

      properties:

        st,spi-midi-ns: false

properties:

  compatible:

    enum:

      - st,stm32f4-spi

      - st,stm32h7-spi

  reg:

    maxItems: 1

  clocks:

    maxItems: 1

  interrupts:

    maxItems: 1

  resets:

    maxItems: 1

  dmas:

    description: |

      DMA specifiers for tx and rx dma. DMA fifo mode must be used. See

      the STM32 DMA bindings Documentation/devicetree/bindings/dma/stm32-dma.txt.

    items:

      - description: rx DMA channel

      - description: tx DMA channel

  dma-names:

    items:

      - const: rx

      - const: tx

patternProperties:

  "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":

    type: object

    # SPI slave nodes must be children of the SPI master node and can

    # contain the following properties.

    properties:

      st,spi-midi-ns:

        description: |

          Only for STM32H7, (Master Inter-Data Idleness) minimum time

          delay in nanoseconds inserted between two consecutive data frames.

required:

  - compatible

  - reg

  - clocks

  - interrupts

examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/stm32mp1-clks.h>

    #include <dt-bindings/reset/stm32mp1-resets.h>

    spi@4000b000 {

      #address-cells = <1>;

      #size-cells = <0>;

      compatible = "st,stm32h7-spi";

      reg = <0x4000b000 0x400>;

      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;

      clocks = <&rcc SPI2_K>;

      resets = <&rcc SPI2_R>;

      dmas = <&dmamux1 0 39 0x400 0x05>,

             <&dmamux1 1 40 0x400 0x05>;

      dma-names = "rx", "tx";

      cs-gpios = <&gpioa 11 0>;

      aardvark@0 {

        compatible = "totalphase,aardvark";

        reg = <0>;

        spi-max-frequency = <4000000>;

        st,spi-midi-ns = <4000>;

      };

    };

...

F:	drivers/scsi/hisi_sas/

F:	Documentation/devicetree/bindings/scsi/hisilicon-sas.txt

HISILICON V3XX SPI NOR FLASH Controller Driver

M:	John Garry <john.garry@huawei.com>

W:	http://www.hisilicon.com

S:	Maintained

F:	drivers/spi/spi-hisi-sfc-v3xx.c

HISILICON QM AND ZIP Controller DRIVER

M:	Zhou Wang <wangzhou1@hisilicon.com>

L:	linux-crypto@vger.kernel.org