Unverified Commit 7507445b authored by Huacai Chen's avatar Huacai Chen Committed by Paul Burton
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MIPS: Loongson: Add Loongson-3A R4 basic support 



All Loongson-3 CPU family:

Code-name         Brand-name       PRId
Loongson-3A R1    Loongson-3A1000  0x6305
Loongson-3A R2    Loongson-3A2000  0x6308
Loongson-3A R2.1  Loongson-3A2000  0x630c
Loongson-3A R3    Loongson-3A3000  0x6309
Loongson-3A R3.1  Loongson-3A3000  0x630d
Loongson-3A R4    Loongson-3A4000  0xc000
Loongson-3B R1    Loongson-3B1000  0x6306
Loongson-3B R2    Loongson-3B1500  0x6307

Features of R4 revision of Loongson-3A:

  - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc.
  - Support variable ASID bits.
  - Support MSA and VZ extensions.
  - Support CPUCFG (CPU config) and CSR (Control and Status Register)
      extensions.
  - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way
      set-associative).

Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is
the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/
2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors
which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R
(e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in
general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G.

Signed-off-by: default avatarHuacai Chen <chenhc@lemote.com>
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-mips@vger.kernel.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Huacai Chen <chenhuacai@gmail.com>
parent 6a6f9b7d

arch/mips/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -1387,9 +1387,11 @@ config CPU_LOONGSON3 
	select CPU_SUPPORTS_64BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HUGEPAGES

	select CPU_SUPPORTS_MSA

	select CPU_HAS_LOAD_STORE_LR

	select WEAK_ORDERING

	select WEAK_REORDERING_BEYOND_LLSC

	select MIPS_ASID_BITS_VARIABLE

	select MIPS_PGD_C0_CONTEXT

	select MIPS_L1_CACHE_SHIFT_6

	select GPIOLIB

arch/mips/include/asm/cpu.h

+3 −1
Original line number Diff line number Diff line
@@ -91,7 +91,9 @@ 
#define PRID_IMP_LOONGSON_32	0x4200  /* Loongson-1 */

#define PRID_IMP_R5432		0x5400

#define PRID_IMP_R5500		0x5500

#define PRID_IMP_LOONGSON_64	0x6300  /* Loongson-2/3 */

#define PRID_IMP_LOONGSON_64R	0x6100  /* Reduced Loongson-2 */

#define PRID_IMP_LOONGSON_64C	0x6300  /* Classic Loongson-2 and Loongson-3 */

#define PRID_IMP_LOONGSON_64G	0xc000  /* Generic Loongson-2 and Loongson-3 */



#define PRID_IMP_UNKNOWN	0xff00

arch/mips/include/asm/mach-loongson64/kernel-entry-init.h

+22 −6
Original line number Diff line number Diff line
@@ -30,13 +30,21 @@ 
	mtc0	t0, CP0_PAGEGRAIN

	/* Enable STFill Buffer */

	mfc0	t0, CP0_PRID

	/* Loongson-3A R4+ */

	andi	t1, t0, PRID_IMP_MASK

	li	t2, PRID_IMP_LOONGSON_64G

	beq     t1, t2, 1f

	nop

	/* Loongson-3A R2/R3 */

	andi	t0, (PRID_IMP_MASK | PRID_REV_MASK)

	slti	t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)

	bnez	t0, 1f

	slti	t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)

	bnez	t0, 2f

	nop

1:

	mfc0	t0, CP0_CONFIG6

	or	t0, 0x100

	mtc0	t0, CP0_CONFIG6

1:

2:

	_ehb

	.set	pop

#endif
@@ -59,13 +67,21 @@ 
	mtc0	t0, CP0_PAGEGRAIN

	/* Enable STFill Buffer */

	mfc0	t0, CP0_PRID

	/* Loongson-3A R4+ */

	andi	t1, t0, PRID_IMP_MASK

	li	t2, PRID_IMP_LOONGSON_64G

	beq     t1, t2, 1f

	nop

	/* Loongson-3A R2/R3 */

	andi	t0, (PRID_IMP_MASK | PRID_REV_MASK)

	slti	t0, (PRID_IMP_LOONGSON_64 | PRID_REV_LOONGSON3A_R2_0)

	bnez	t0, 1f

	slti	t0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0)

	bnez	t0, 2f

	nop

1:

	mfc0	t0, CP0_CONFIG6

	or	t0, 0x100

	mtc0	t0, CP0_CONFIG6

1:

2:

	_ehb

	.set	pop

#endif

arch/mips/kernel/cpu-probe.c

+14 −2
Original line number Diff line number Diff line
@@ -1526,7 +1526,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 
			     MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;

		c->tlbsize = 64;

		break;

	case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */

	case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */

		switch (c->processor_id & PRID_REV_MASK) {

		case PRID_REV_LOONGSON2E:

			c->cputype = CPU_LOONGSON2;
@@ -1565,6 +1565,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 
			     MIPS_CPU_FPU | MIPS_CPU_LLSC |

			     MIPS_CPU_32FPR;

		c->tlbsize = 64;

		set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		break;

	case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
@@ -1903,7 +1904,7 @@ platform: 
static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)

{

	switch (c->processor_id & PRID_IMP_MASK) {

	case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */

	case PRID_IMP_LOONGSON_64C:  /* Loongson-2/3 */

		switch (c->processor_id & PRID_REV_MASK) {

		case PRID_REV_LOONGSON3A_R2_0:

		case PRID_REV_LOONGSON3A_R2_1:
@@ -1921,6 +1922,17 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) 
			break;

		}



		decode_configs(c);

		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

		c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |

			MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);

		break;

	case PRID_IMP_LOONGSON_64G:

		c->cputype = CPU_LOONGSON3;

		__cpu_name[cpu] = "ICT Loongson-3";

		set_elf_platform(cpu, "loongson3a");

		set_isa(c, MIPS_CPU_ISA_M64R2);

		decode_configs(c);

		c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;

		c->writecombine = _CACHE_UNCACHED_ACCELERATED;

arch/mips/kernel/idle.c

+2 −1
Original line number Diff line number Diff line
@@ -179,7 +179,8 @@ void __init check_wait(void) 
		cpu_wait = r4k_wait;

		break;

	case CPU_LOONGSON3:

		if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_LOONGSON3A_R2_0)

		if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >=

				(PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3A_R2_0))

			cpu_wait = r4k_wait;

		break;

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