Commit 75037500 authored by Khalid Aziz's avatar Khalid Aziz Committed by David S. Miller
Browse files

sparc64: Add support for ADI register fields, ASIs and traps 



SPARC M7 processor adds new control register fields, ASIs and a new
trap to support the ADI (Application Data Integrity) feature. This
patch adds definitions for these register fields, ASIs and a handler
for the new precise memory corruption detected trap.

Signed-off-by: default avatarKhalid Aziz <khalid.aziz@oracle.com>
Cc: Khalid Aziz <khalid@gonehiking.org>
Reviewed-by: default avatarAnthony Yznaga <anthony.yznaga@oracle.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ca827d55

arch/sparc/include/asm/hypervisor.h

+2 −0
Original line number Diff line number Diff line
@@ -570,6 +570,8 @@ struct hv_fault_status { 
#define HV_FAULT_TYPE_RESV1	13

#define HV_FAULT_TYPE_UNALIGNED	14

#define HV_FAULT_TYPE_INV_PGSZ	15

#define HV_FAULT_TYPE_MCD	17

#define HV_FAULT_TYPE_MCD_DIS	18

/* Values 16 --> -2 are reserved.  */

#define HV_FAULT_TYPE_MULTIPLE	-1

arch/sparc/include/asm/pgtable_64.h

+2 −0
Original line number Diff line number Diff line
@@ -164,6 +164,8 @@ bool kern_addr_valid(unsigned long addr); 
#define _PAGE_E_4V	  _AC(0x0000000000000800,UL) /* side-Effect          */

#define _PAGE_CP_4V	  _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */

#define _PAGE_CV_4V	  _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */

/* Bit 9 is used to enable MCD corruption detection instead on M7 */

#define _PAGE_MCD_4V      _AC(0x0000000000000200,UL) /* Memory Corruption    */

#define _PAGE_P_4V	  _AC(0x0000000000000100,UL) /* Privileged Page      */

#define _PAGE_EXEC_4V	  _AC(0x0000000000000080,UL) /* Executable Page      */

#define _PAGE_W_4V	  _AC(0x0000000000000040,UL) /* Writable             */

arch/sparc/include/asm/ttable.h

+10 −0
Original line number Diff line number Diff line
@@ -219,6 +219,16 @@ 
	nop;						\

	nop;



#define SUN4V_MCD_PRECISE				\

	ldxa	[%g0] ASI_SCRATCHPAD, %g2;		\

	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4;	\

	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5;	\

	ba,pt	%xcc, etrap;				\

	 rd	%pc, %g7;				\

	ba,pt	%xcc, sun4v_mcd_detect_precise;		\

	 nop;						\

	nop;



/* Before touching these macros, you owe it to yourself to go and

 * see how arch/sparc64/kernel/winfixup.S works... -DaveM

 *

arch/sparc/include/uapi/asm/asi.h

+5 −0
Original line number Diff line number Diff line
@@ -145,6 +145,8 @@ 
 * ASIs, "(4V)" designates SUN4V specific ASIs.  "(NG4)" designates SPARC-T4

 * and later ASIs.

 */

#define ASI_MCD_PRIV_PRIMARY	0x02 /* (NG7) Privileged MCD version VA	*/

#define ASI_MCD_REAL		0x05 /* (NG7) Privileged MCD version PA	*/

#define ASI_PHYS_USE_EC		0x14 /* PADDR, E-cachable		*/

#define ASI_PHYS_BYPASS_EC_E	0x15 /* PADDR, E-bit			*/

#define ASI_BLK_AIUP_4V		0x16 /* (4V) Prim, user, block ld/st	*/
@@ -245,6 +247,9 @@ 
#define ASI_UDBL_CONTROL_R	0x7f /* External UDB control regs rd low*/

#define ASI_INTR_R		0x7f /* IRQ vector dispatch read	*/

#define ASI_INTR_DATAN_R	0x7f /* (III) In irq vector data reg N	*/

#define ASI_MCD_PRIMARY		0x90 /* (NG7) MCD version load/store	*/

#define ASI_MCD_ST_BLKINIT_PRIMARY	\

				0x92 /* (NG7) MCD store BLKINIT primary	*/

#define ASI_PIC			0xb0 /* (NG4) PIC registers		*/

#define ASI_PST8_P		0xc0 /* Primary, 8 8-bit, partial	*/

#define ASI_PST8_S		0xc1 /* Secondary, 8 8-bit, partial	*/

arch/sparc/include/uapi/asm/pstate.h

+10 −0
Original line number Diff line number Diff line
@@ -11,7 +11,12 @@ 
 * -----------------------------------------------------------------------

 *  63  12  11   10    9     8    7   6   5     4     3     2     1    0

 */

/* IG on V9 conflicts with MCDE on M7. PSTATE_MCDE will only be used on

 * processors that support ADI which do not use IG, hence there is no

 * functional conflict

 */

#define PSTATE_IG   _AC(0x0000000000000800,UL) /* Interrupt Globals.	*/

#define PSTATE_MCDE _AC(0x0000000000000800,UL) /* MCD Enable		*/

#define PSTATE_MG   _AC(0x0000000000000400,UL) /* MMU Globals.		*/

#define PSTATE_CLE  _AC(0x0000000000000200,UL) /* Current Little Endian.*/

#define PSTATE_TLE  _AC(0x0000000000000100,UL) /* Trap Little Endian.	*/
@@ -48,7 +53,12 @@ 
#define TSTATE_ASI	_AC(0x00000000ff000000,UL) /* AddrSpace ID.	*/

#define TSTATE_PIL	_AC(0x0000000000f00000,UL) /* %pil (Linux traps)*/

#define TSTATE_PSTATE	_AC(0x00000000000fff00,UL) /* PSTATE.		*/

/* IG on V9 conflicts with MCDE on M7. TSTATE_MCDE will only be used on

 * processors that support ADI which do not support IG, hence there is

 * no functional conflict

 */

#define TSTATE_IG	_AC(0x0000000000080000,UL) /* Interrupt Globals.*/

#define TSTATE_MCDE	_AC(0x0000000000080000,UL) /* MCD enable.       */

#define TSTATE_MG	_AC(0x0000000000040000,UL) /* MMU Globals.	*/

#define TSTATE_CLE	_AC(0x0000000000020000,UL) /* CurrLittleEndian.	*/

#define TSTATE_TLE	_AC(0x0000000000010000,UL) /* TrapLittleEndian.	*/

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