iommu/arm-smmu: Enable bypass transaction caching for ARM SMMU 500 (74f55d34) · Commits · 戴 / test

The ARM SMMU identity mapping performance was poor compared with the DMA mode. It was found that enable caching would restore the performance back to normal. The S2CRB_TLBEN bit in the ACR register would allow for caching of the stream to context register bypass transaction information. Reviewed-by:

Robin Murphy <robin.murphy@arm.com> Signed-off-by:

Feng Kan <fkan@apm.com> Signed-off-by:

Will Deacon <will.deacon@arm.com>

drivers/iommu/arm-smmu.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -59,6 +59,7 @@
		#define ARM_MMU500_ACTLR_CPRE (1 << 1)

		#define ARM_MMU500_ACR_CACHE_LOCK (1 << 26)
		#define ARM_MMU500_ACR_S2CRB_TLBEN (1 << 10)
		#define ARM_MMU500_ACR_SMTNMB_TLBEN (1 << 8)

		#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
		@@ -1598,7 +1599,7 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
		* Allow unmatched Stream IDs to allocate bypass
		* TLB entries for reduced latency.
		*/
		reg \|= ARM_MMU500_ACR_SMTNMB_TLBEN;
		reg \|= ARM_MMU500_ACR_SMTNMB_TLBEN \| ARM_MMU500_ACR_S2CRB_TLBEN;
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
		}

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