Commit 74e29703 authored Mar 03, 2020 by Grygorii Strashko Committed by Kishon Vijay Abraham I Mar 20, 2020

dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc



TI AM654x/J721E SoCs have the same PHY interface selection mechanism for
CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields
placement is different.

This patch adds corresponding compatible strings to enable support for TI
AM654x/J721E SoCs.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

parent 6076967a

Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -40,6 +40,7 @@ Required properties:
		"ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform
		"ti,am43xx-phy-gmii-sel" for am43xx platform
		"ti,dm814-phy-gmii-sel" for dm814x platform
		"ti,am654-phy-gmii-sel" for AM654x/J721E platform
		- reg : Address and length of the register set for the device
		- #phy-cells : must be 2.
		cell 1 - CPSW port number (starting from 1)

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