Commit 74b2089a authored by Michał Winiarski's avatar Michał Winiarski Committed by Chris Wilson
Browse files

drm/i915: Add definitions for MI_MATH command 



We can use it in i915 for updating parts of unmasked registers from
within a batch. We're also adding Gen8+ versions of CS_GPR registers
(aka MI_MATH_REG in the coprocessor).

Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190926100635.9416-4-michal.winiarski@intel.com
parent 56316cbc

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

+23 −0
Original line number Diff line number Diff line
@@ -241,6 +241,29 @@ 
#define   PIPE_CONTROL_DEPTH_CACHE_FLUSH		(1<<0)

#define   PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */



#define MI_MATH(x)			MI_INSTR(0x1a, (x) - 1)

#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))

/* Opcodes for MI_MATH_INSTR */

#define   MI_MATH_NOOP			MI_MATH_INSTR(0x000, 0x0, 0x0)

#define   MI_MATH_LOAD(op1, op2)	MI_MATH_INSTR(0x080, op1, op2)

#define   MI_MATH_LOADINV(op1, op2)	MI_MATH_INSTR(0x480, op1, op2)

#define   MI_MATH_LOAD0(op1)		MI_MATH_INSTR(0x081, op1)

#define   MI_MATH_LOAD1(op1)		MI_MATH_INSTR(0x481, op1)

#define   MI_MATH_ADD			MI_MATH_INSTR(0x100, 0x0, 0x0)

#define   MI_MATH_SUB			MI_MATH_INSTR(0x101, 0x0, 0x0)

#define   MI_MATH_AND			MI_MATH_INSTR(0x102, 0x0, 0x0)

#define   MI_MATH_OR			MI_MATH_INSTR(0x103, 0x0, 0x0)

#define   MI_MATH_XOR			MI_MATH_INSTR(0x104, 0x0, 0x0)

#define   MI_MATH_STORE(op1, op2)	MI_MATH_INSTR(0x180, op1, op2)

#define   MI_MATH_STOREINV(op1, op2)	MI_MATH_INSTR(0x580, op1, op2)

/* Registers used as operands in MI_MATH_INSTR */

#define   MI_MATH_REG(x)		(x)

#define   MI_MATH_REG_SRCA		0x20

#define   MI_MATH_REG_SRCB		0x21

#define   MI_MATH_REG_ACCU		0x31

#define   MI_MATH_REG_ZF		0x32

#define   MI_MATH_REG_CF		0x33



/*

 * Commands used only by the command parser

 */

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -2483,6 +2483,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   RING_WAIT		(1 << 11) /* gen3+, PRBx_CTL */

#define   RING_WAIT_SEMAPHORE	(1 << 10) /* gen6+ */



/* There are 16 64-bit CS General Purpose Registers per-engine on Gen8+ */

#define GEN8_RING_CS_GPR(base, n)	_MMIO((base) + 0x600 + (n) * 8)

#define GEN8_RING_CS_GPR_UDW(base, n)	_MMIO((base) + 0x600 + (n) * 8 + 4)



#define RING_FORCE_TO_NONPRIV(base, i) _MMIO(((base) + 0x4D0) + (i) * 4)

#define   RING_FORCE_TO_NONPRIV_ACCESS_RW	(0 << 28)    /* CFL+ & Gen11+ */

#define   RING_FORCE_TO_NONPRIV_ACCESS_RD	(1 << 28)

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