ARM: davinci: aintc: use irq domain (74b0eac2) · Commits · 戴 / test

arch/arm/mach-davinci/irq.c

+27 −8

Original line number	Diff line number	Diff line
		@@ -23,6 +23,7 @@
		#include <linux/interrupt.h>
		#include <linux/irq.h>
		#include <linux/io.h>
		#include <linux/irqdomain.h>

		#include <mach/hardware.h>
		#include <mach/cputype.h>
		@@ -40,23 +41,23 @@
		#define IRQ_INTPRI0_REG_OFFSET 0x0030
		#define IRQ_INTPRI7_REG_OFFSET 0x004C

		static struct irq_domain *davinci_irq_domain;

		static inline void davinci_irq_writel(unsigned long value, int offset)
		{
		__raw_writel(value, davinci_intc_base + offset);
		}

		static __init void
		davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
		davinci_irq_setup_gc(void __iomem *base,
		unsigned int irq_start, unsigned int num)
		{
		struct irq_chip_generic *gc;
		struct irq_chip_type *ct;

		gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
		if (!gc) {
		pr_err("%s: irq_alloc_generic_chip for IRQ %u failed\n",
		__func__, irq_start);
		return;
		}
		gc = irq_get_domain_generic_chip(davinci_irq_domain, irq_start);
		gc->reg_base = base;
		gc->irq_base = irq_start;

		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		@@ -74,6 +75,7 @@ void __init davinci_irq_init(void)
		{
		unsigned i, j;
		const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
		int ret, irq_base;

		davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
		davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
		@@ -110,8 +112,25 @@ void __init davinci_irq_init(void)
		davinci_irq_writel(pri, i);
		}

		irq_base = irq_alloc_descs(-1, 0, davinci_soc_info.intc_irq_num, 0);
		if (WARN_ON(irq_base < 0))
		return;

		davinci_irq_domain = irq_domain_add_legacy(NULL,
		davinci_soc_info.intc_irq_num,
		irq_base, 0, &irq_domain_simple_ops,
		NULL);
		if (WARN_ON(!davinci_irq_domain))
		return;

		ret = irq_alloc_domain_generic_chips(davinci_irq_domain, 32, 1,
		"AINTC", handle_edge_irq,
		IRQ_NOREQUEST \| IRQ_NOPROBE, 0, 0);
		if (WARN_ON(ret))
		return;

		for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
		davinci_alloc_gc(davinci_intc_base + j, i, 32);
		davinci_irq_setup_gc(davinci_intc_base + j, irq_base + i, 32);

		irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
		}

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