Commit 74ab8ccf authored by Kathiravan T's avatar Kathiravan T Committed by Bjorn Andersson
Browse files

arm64: dts: ipq6018: Add the QPIC peripheral nodes 



Add the QPIC BAM and QPIC NAND controller support and
enable the same in board DTS file.

Co-developed-by: default avatarAnusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Signed-off-by: default avatarAnusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Signed-off-by: default avatarKathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent fbdb20b1

arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts

+16 −0
Original line number Diff line number Diff line
@@ -62,3 +62,19 @@ 
		bias-pull-down;

	};

};



&qpic_bam {

	status = "okay";

};



&qpic_nand {

	status = "okay";



	nand@0 {

		reg = <0>;



		nand-ecc-strength = <4>;

		nand-ecc-step-size = <512>;

		nand-bus-width = <8>;

	};

};

arch/arm64/boot/dts/qcom/ipq6018.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -231,6 +231,17 @@ 
				drive-strength = <8>;

				bias-pull-down;

			};



			qpic_pins: qpic-pins {

				pins = "gpio1", "gpio3", "gpio4",

					"gpio5", "gpio6", "gpio7",

					"gpio8", "gpio10", "gpio11",

					"gpio12", "gpio13", "gpio14",

					"gpio15", "gpio17";

				function = "qpic_pad";

				drive-strength = <8>;

				bias-disable;

			};

		};



		gcc: gcc@1800000 {
@@ -332,6 +343,36 @@ 
			status = "disabled";

		};



		qpic_bam: dma-controller@7984000 {

			compatible = "qcom,bam-v1.7.0";

			reg = <0x0 0x07984000 0x0 0x1a000>;

			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_QPIC_CLK>,

				 <&gcc GCC_QPIC_AHB_CLK>;

			clock-names = "iface_clk", "bam_clk";

			#dma-cells = <1>;

			qcom,ee = <0>;

			status = "disabled";

		};



		qpic_nand: nand@79b0000 {

			compatible = "qcom,ipq6018-nand";

			reg = <0x0 0x079b0000 0x0 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&gcc GCC_QPIC_CLK>,

				 <&gcc GCC_QPIC_AHB_CLK>;

			clock-names = "core", "aon";



			dmas = <&qpic_bam 0>,

				<&qpic_bam 1>,

				<&qpic_bam 2>;

			dma-names = "tx", "rx", "cmd";

			pinctrl-0 = <&qpic_pins>;

			pinctrl-names = "default";

			status = "disabled";

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

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