net: phy: dp83867: w/a for fld detect threshold bootstrapping issue (749f6f68) · Commits · 戴 / test

drivers/net/phy/dp83867.c

+20 −1

Original line number	Diff line number	Diff line
		@@ -28,6 +28,7 @@
		#define DP83867_CTRL 0x1f

		/* Extended Registers */
		#define DP83867_FLD_THR_CFG 0x002e
		#define DP83867_CFG4 0x0031
		#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) \| BIT(6))
		#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
		@@ -91,6 +92,7 @@
		#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
		#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
		#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
		#define DP83867_STRAP_STS2_STRAP_FLD BIT(10)

		/* PHY CTRL bits */
		#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT 14
		@@ -125,6 +127,9 @@
		/* CFG4 bits */
		#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)

		/* FLD_THR_CFG */
		#define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK 0x7

		enum {
		DP83867_PORT_MIRROING_KEEP,
		DP83867_PORT_MIRROING_EN,
		@@ -476,6 +481,20 @@ static int dp83867_config_init(struct phy_device *phydev)
		phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
		BIT(7));

		bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
		if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
		/* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
		* be set to 0x2. This may causes the PHY link to be unstable -
		* the default value 0x1 need to be restored.
		*/
		ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
		DP83867_FLD_THR_CFG,
		DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
		0x1);
		if (ret)
		return ret;
		}

		if (phy_interface_is_rgmii(phydev) \|\|
		phydev->interface == PHY_INTERFACE_MODE_SGMII) {
		val = phy_read(phydev, MII_DP83867_PHYCTRL);