KVM: ARM: Initial skeleton to compile KVM support (749cf76c) · Commits · 戴 / test

Documentation/virtual/kvm/api.txt

+53 −4

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		@@ -293,7 +293,7 @@ kvm_run' (see below).
		4.11 KVM_GET_REGS

		Capability: basic
		Architectures: all
		Architectures: all except ARM
		Type: vcpu ioctl
		Parameters: struct kvm_regs (out)
		Returns: 0 on success, -1 on error
		@@ -314,7 +314,7 @@ struct kvm_regs {
		4.12 KVM_SET_REGS

		Capability: basic
		Architectures: all
		Architectures: all except ARM
		Type: vcpu ioctl
		Parameters: struct kvm_regs (in)
		Returns: 0 on success, -1 on error
		@@ -600,7 +600,7 @@ struct kvm_fpu {
		4.24 KVM_CREATE_IRQCHIP

		Capability: KVM_CAP_IRQCHIP
		Architectures: x86, ia64
		Architectures: x86, ia64, ARM
		Type: vm ioctl
		Parameters: none
		Returns: 0 on success, -1 on error
		@@ -608,7 +608,8 @@ Returns: 0 on success, -1 on error
		Creates an interrupt controller model in the kernel. On x86, creates a virtual
		ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a
		local APIC. IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23
		only go to the IOAPIC. On ia64, a IOSAPIC is created.
		only go to the IOAPIC. On ia64, a IOSAPIC is created. On ARM, a GIC is
		created.


		4.25 KVM_IRQ_LINE
		@@ -1775,6 +1776,14 @@ registers, find a list below:
		PPC \| KVM_REG_PPC_VPA_DTL \| 128
		PPC \| KVM_REG_PPC_EPCR \| 32

		ARM registers are mapped using the lower 32 bits. The upper 16 of that
		is the register group type, or coprocessor number:

		ARM core registers have the following id bit patterns:
		0x4002 0000 0010 <index into the kvm_regs struct:16>



		4.69 KVM_GET_ONE_REG

		Capability: KVM_CAP_ONE_REG
		@@ -2127,6 +2136,46 @@ written, then `n_invalid' invalid entries, invalidating any previously
		valid entries found.


		4.77 KVM_ARM_VCPU_INIT

		Capability: basic
		Architectures: arm
		Type: vcpu ioctl
		Parameters: struct struct kvm_vcpu_init (in)
		Returns: 0 on success; -1 on error
		Errors:
		EINVAL: the target is unknown, or the combination of features is invalid.
		ENOENT: a features bit specified is unknown.

		This tells KVM what type of CPU to present to the guest, and what
		optional features it should have. This will cause a reset of the cpu
		registers to their initial values. If this is not called, KVM_RUN will
		return ENOEXEC for that vcpu.

		Note that because some registers reflect machine topology, all vcpus
		should be created before this ioctl is invoked.


		4.78 KVM_GET_REG_LIST

		Capability: basic
		Architectures: arm
		Type: vcpu ioctl
		Parameters: struct kvm_reg_list (in/out)
		Returns: 0 on success; -1 on error
		Errors:
		E2BIG: the reg index list is too big to fit in the array specified by
		the user (the number required will be written into n).

		struct kvm_reg_list {
		__u64 n; /* number of registers in reg[] */
		__u64 reg[0];
		};

		This ioctl returns the guest registers that are supported for the
		KVM_GET_ONE_REG/KVM_SET_ONE_REG calls.


		5. The kvm_run structure
		------------------------

arch/arm/Kconfig

+2 −0

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		@@ -2322,3 +2322,5 @@ source "security/Kconfig"
		source "crypto/Kconfig"

		source "lib/Kconfig"

		source "arch/arm/kvm/Kconfig"

arch/arm/Makefile

+1 −0

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		@@ -252,6 +252,7 @@ core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
		core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
		core-$(CONFIG_VFP) += arch/arm/vfp/
		core-$(CONFIG_XEN) += arch/arm/xen/
		core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/

		# If we have a machine-specific directory, then include it in the build.
		core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/

arch/arm/include/asm/kvm_arm.h

0 → 100644

+24 −0

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		/*
		* Copyright (C) 2012 - Virtual Open Systems and Columbia University
		* Author: Christoffer Dall <c.dall@virtualopensystems.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License, version 2, as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
		*/

		#ifndef __ARM_KVM_ARM_H__
		#define __ARM_KVM_ARM_H__

		#include <linux/types.h>

		#endif /* __ARM_KVM_ARM_H__ */

arch/arm/include/asm/kvm_asm.h

0 → 100644

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		/*
		* Copyright (C) 2012 - Virtual Open Systems and Columbia University
		* Author: Christoffer Dall <c.dall@virtualopensystems.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License, version 2, as
		* published by the Free Software Foundation.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
		*/

		#ifndef __ARM_KVM_ASM_H__
		#define __ARM_KVM_ASM_H__

		/* 0 is reserved as an invalid value. */
		#define c0_MPIDR 1 /* MultiProcessor ID Register */
		#define c0_CSSELR 2 /* Cache Size Selection Register */
		#define c1_SCTLR 3 /* System Control Register */
		#define c1_ACTLR 4 /* Auxilliary Control Register */
		#define c1_CPACR 5 /* Coprocessor Access Control */
		#define c2_TTBR0 6 /* Translation Table Base Register 0 */
		#define c2_TTBR0_high 7 /* TTBR0 top 32 bits */
		#define c2_TTBR1 8 /* Translation Table Base Register 1 */
		#define c2_TTBR1_high 9 /* TTBR1 top 32 bits */
		#define c2_TTBCR 10 /* Translation Table Base Control R. */
		#define c3_DACR 11 /* Domain Access Control Register */
		#define c5_DFSR 12 /* Data Fault Status Register */
		#define c5_IFSR 13 /* Instruction Fault Status Register */
		#define c5_ADFSR 14 /* Auxilary Data Fault Status R */
		#define c5_AIFSR 15 /* Auxilary Instrunction Fault Status R */
		#define c6_DFAR 16 /* Data Fault Address Register */
		#define c6_IFAR 17 /* Instruction Fault Address Register */
		#define c9_L2CTLR 18 /* Cortex A15 L2 Control Register */
		#define c10_PRRR 19 /* Primary Region Remap Register */
		#define c10_NMRR 20 /* Normal Memory Remap Register */
		#define c12_VBAR 21 /* Vector Base Address Register */
		#define c13_CID 22 /* Context ID Register */
		#define c13_TID_URW 23 /* Thread ID, User R/W */
		#define c13_TID_URO 24 /* Thread ID, User R/O */
		#define c13_TID_PRIV 25 /* Thread ID, Privileged */
		#define NR_CP15_REGS 26 /* Number of regs (incl. invalid) */

		#define ARM_EXCEPTION_RESET 0
		#define ARM_EXCEPTION_UNDEFINED 1
		#define ARM_EXCEPTION_SOFTWARE 2
		#define ARM_EXCEPTION_PREF_ABORT 3
		#define ARM_EXCEPTION_DATA_ABORT 4
		#define ARM_EXCEPTION_IRQ 5
		#define ARM_EXCEPTION_FIQ 6

		#endif /* __ARM_KVM_ASM_H__ */

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