Commit 74689ddf authored Sep 11, 2019 by Ville Syrjälä Committed by Chris Wilson Sep 12, 2019

drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glk



On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.

Cc: Matt Roper <matthew.d.roper@intel.com>
Fixes: 71dc367e ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190911133129.27466-1-ville.syrjala@linux.intel.com

parent 24977870

drivers/gpu/drm/i915/display/intel_cdclk.c

+2 −1

Original line number	Diff line number	Diff line
		@@ -1351,6 +1351,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
		u32 divider;
		int div;

		bxt_de_pll_readout(dev_priv, cdclk_state);

		if (INTEL_GEN(dev_priv) >= 12)
		cdclk_state->bypass = cdclk_state->ref / 2;
		else if (INTEL_GEN(dev_priv) >= 11)
		@@ -1358,7 +1360,6 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
		else
		cdclk_state->bypass = cdclk_state->ref;

		bxt_de_pll_readout(dev_priv, cdclk_state);
		if (cdclk_state->vco == 0) {
		cdclk_state->cdclk = cdclk_state->bypass;
		goto out;

Admin message