Commit 7436830c authored by Valtteri Rantala's avatar Valtteri Rantala Committed by Imre Deak
Browse files

drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too 



Testing the texture read performance shows that the same tuning for
the SQ credits is needed on GLK as on BXT/APL. This has been also
confirmed by Altug from the HW team.

V4: Rebase + fix
Signed-off-by: default avatarValtteri Rantala <valtteri.rantala@intel.com>
Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> (v1)
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1511880305-12166-1-git-send-email-valtteri.rantala@intel.com
parent cc440856

drivers/gpu/drm/i915/intel_engine_cs.c

+9 −7
Original line number Diff line number Diff line
@@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) 
	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */

	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);



	/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */

	if (IS_GEN9_LP(dev_priv)) {

		u32 val = I915_READ(GEN8_L3SQCREG1);



		val &= ~L3_PRIO_CREDITS_MASK;

		val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);

		I915_WRITE(GEN8_L3SQCREG1, val);

	}



	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */

	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |

				    GEN8_LQSC_FLUSH_COHERENT_LINES));
@@ -1184,7 +1193,6 @@ static int skl_init_workarounds(struct intel_engine_cs *engine) 
static int bxt_init_workarounds(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	u32 val;

	int ret;



	ret = gen9_init_workarounds(engine);
@@ -1199,12 +1207,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) 
	I915_WRITE(FF_SLICE_CS_CHICKEN2,

		   _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));



	/* WaProgramL3SqcReg1DefaultForPerf:bxt */

	val = I915_READ(GEN8_L3SQCREG1);

	val &= ~L3_PRIO_CREDITS_MASK;

	val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);

	I915_WRITE(GEN8_L3SQCREG1, val);



	/* WaToEnableHwFixForPushConstHWBug:bxt */

	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,

			  GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);

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