spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change (742d5958) · Commits · 戴 / test

As per the spi core implementation for MSPI devices when the transfer is the last one in the message, the chip may stay selected until the next transfer. On multi-device SPI busses with nothing blocking messages going to other devices, this is just a performance hint; starting a message to another device deselects this one. But in other cases, this can be used to ensure correctness. Some devices need protocol transactions to be built from a series of spi_message submissions, where the content of one message is determined by the results of previous messages and where the whole transaction ends when the chipselect goes intactive. On CS change after completing the last serial transfer, the MSPI driver drives SSb pin CDRAM register correctly according comments in core spi.h as shown below: case 1) EOM =1, cs_change =0: SSb inactive case 2) EOM =1, cs_change =1: SSb active case 3) EOM =0, cs_change =0: SSb active case 4) EOM =0, cs_change =1: SSb inactive Signed-off-by:

Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20200420190853.45614-5-kdasu.kdev@gmail.com Signed-off-by:

Mark Brown <broonie@kernel.org>

drivers/spi/spi-bcm-qspi.c

+12 −7

Original line number	Diff line number	Diff line
		@@ -612,19 +612,15 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
		if (qt->trans->cs_change &&
		(flags & TRANS_STATUS_BREAK_CS_CHANGE))
		ret \|= TRANS_STATUS_BREAK_CS_CHANGE;
		if (ret)
		goto done;

		dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
		if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
		ret = TRANS_STATUS_BREAK_EOM;
		ret \|= TRANS_STATUS_BREAK_EOM;
		else
		ret = TRANS_STATUS_BREAK_NO_BYTES;
		ret \|= TRANS_STATUS_BREAK_NO_BYTES;

		qt->trans = NULL;
		}

		done:
		dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
		qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
		return ret;
		@@ -771,7 +767,16 @@ static int write_to_hw(struct bcm_qspi qspi, struct spi_device spi)
		bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
		bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);

		if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
		/*
		* case 1) EOM =1, cs_change =0: SSb inactive
		* case 2) EOM =1, cs_change =1: SSb stay active
		* case 3) EOM =0, cs_change =0: SSb stay active
		* case 4) EOM =0, cs_change =1: SSb inactive
		*/
		if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
		== TRANS_STATUS_BREAK_CS_CHANGE) \|\|
		((tstatus & TRANS_STATUS_BREAK_DESELECT)
		== TRANS_STATUS_BREAK_EOM)) {
		mspi_cdram = read_cdram_slot(qspi, slot - 1) &
		~MSPI_CDRAM_CONT_BIT;
		write_cdram_slot(qspi, slot - 1, mspi_cdram);

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