Commit 73d6bd7a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branch 'clk-qcom' into clk-next 

* clk-qcom:
  clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
  ipq806x: gcc: add support for child probe
  clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
  clk: qcom: ipq8074: Add correct index for PCIe clocks
parents 46e3ecda 9c3df2b1

drivers/clk/qcom/clk-cpu-8996.c

+1 −1
Original line number Diff line number Diff line
@@ -338,7 +338,7 @@ static const struct regmap_config cpu_msm8996_regmap_config = { 
	.val_format_endian	= REGMAP_ENDIAN_LITTLE,

};



struct clk_regmap *cpu_msm8996_clks[] = {

static struct clk_regmap *cpu_msm8996_clks[] = {

	&perfcl_pll.clkr,

	&pwrcl_pll.clkr,

	&perfcl_alt_pll.clkr,

drivers/clk/qcom/gcc-ipq806x.c

+1 −1
Original line number Diff line number Diff line
@@ -3089,7 +3089,7 @@ static int gcc_ipq806x_probe(struct platform_device *pdev) 
	regmap_write(regmap, 0x3cf8, 8);

	regmap_write(regmap, 0x3d18, 8);



	return 0;

	return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);

}



static struct platform_driver gcc_ipq806x_driver = {

drivers/clk/qcom/gcc-sc7180.c

+1 −1
Original line number Diff line number Diff line
@@ -1061,7 +1061,7 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { 
				.hw = &gpll0.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

			.ops = &clk_branch2_aon_ops,

		},

	},

};

drivers/clk/qcom/gcc-sdm845.c

+2 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.

 */



#include <linux/kernel.h>
@@ -1344,7 +1344,7 @@ static struct clk_branch gcc_disp_gpll0_clk_src = { 
				"gpll0",

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

			.ops = &clk_branch2_aon_ops,

		},

	},

};

include/dt-bindings/clock/qcom,gcc-ipq8074.h

+3 −3
Original line number Diff line number Diff line
@@ -230,6 +230,9 @@ 
#define GCC_GP1_CLK				221

#define GCC_GP2_CLK				222

#define GCC_GP3_CLK				223

#define GCC_PCIE0_AXI_S_BRIDGE_CLK		224

#define GCC_PCIE0_RCHNG_CLK_SRC			225

#define GCC_PCIE0_RCHNG_CLK			226



#define GCC_BLSP1_BCR				0

#define GCC_BLSP1_QUP1_BCR			1
@@ -363,8 +366,5 @@ 
#define GCC_PCIE1_AHB_ARES			129

#define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130

#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131

#define GCC_PCIE0_AXI_S_BRIDGE_CLK		132

#define GCC_PCIE0_RCHNG_CLK_SRC			133

#define GCC_PCIE0_RCHNG_CLK			134



#endif

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