ASoC: fsl_esai: Add indentation for binding doc to increase readability

  - clock-names		: Includes the following entries:

	"core"		  The core clock used to access registers

	"extal"		The esai baud clock for esai controller used to derive

			HCK, SCK and FS.

	"fsys"		The system clock derived from ahb clock used to derive

			HCK, SCK and FS.

	"extal"		  The esai baud clock for esai controller used to

			  derive HCK, SCK and FS.

	"fsys"		  The system clock derived from ahb clock used to

			  derive HCK, SCK and FS.

  - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.

    This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].

  - fsl,fifo-depth	: The number of elements in the transmit and receive

			  FIFOs. This number is the maximum allowed value for

			  TFCR[TFWM] or RFCR[RFWM].

  - fsl,esai-synchronous: This is a boolean property. If present, indicating

    that ESAI would work in the synchronous mode, which means all the settings

    for Receiving would be duplicated from Transmition related registers.

			  that ESAI would work in the synchronous mode, which

			  means all the settings for Receiving would be

			  duplicated from Transmition related registers.

  - big-endian : If this property is absent, the native endian mode will

    be in use as default, or the big endian mode will be in use for all the

    device registers.

  - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example: