drm/i915: small isolated c99 types to kernel types switch (739f3abd) · Commits · 戴 / test

drivers/gpu/drm/i915/i915_gem.c

+7 −7

Original line number	Diff line number	Diff line
		@@ -713,8 +713,8 @@ void i915_gem_object_free(struct drm_i915_gem_object *obj)
		static int
		i915_gem_create(struct drm_file *file,
		struct drm_i915_private *dev_priv,
		uint64_t size,
		uint32_t *handle_p)
		u64 size,
		u32 *handle_p)
		{
		struct drm_i915_gem_object *obj;
		int ret;
		@@ -1573,8 +1573,8 @@ i915_gem_set_domain_ioctl(struct drm_device dev, void data,
		{
		struct drm_i915_gem_set_domain *args = data;
		struct drm_i915_gem_object *obj;
		uint32_t read_domains = args->read_domains;
		uint32_t write_domain = args->write_domain;
		u32 read_domains = args->read_domains;
		u32 write_domain = args->write_domain;
		int err;

		/* Only handle setting domains to types used by the CPU. */
		@@ -1756,7 +1756,7 @@ i915_gem_mmap_ioctl(struct drm_device dev, void data,
		if (IS_ERR((void *)addr))
		return addr;

		args->addr_ptr = (uint64_t) addr;
		args->addr_ptr = (u64)addr;

		return 0;
		}
		@@ -2158,8 +2158,8 @@ static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
		int
		i915_gem_mmap_gtt(struct drm_file *file,
		struct drm_device *dev,
		uint32_t handle,
		uint64_t *offset)
		u32 handle,
		u64 *offset)
		{
		struct drm_i915_gem_object *obj;
		int ret;

+4 −4

Original line number	Diff line number	Diff line
		@@ -555,8 +555,8 @@ void i915_gem_restore_fences(struct drm_i915_private *dev_priv)
		void
		i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
		{
		uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
		uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
		u32 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
		u32 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;

		if (INTEL_GEN(dev_priv) >= 8 \|\| IS_VALLEYVIEW(dev_priv)) {
		/*
		@@ -579,7 +579,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		}
		} else {
		uint32_t dimm_c0, dimm_c1;
		u32 dimm_c0, dimm_c1;
		dimm_c0 = I915_READ(MAD_DIMM_C0);
		dimm_c1 = I915_READ(MAD_DIMM_C1);
		dimm_c0 &= MAD_DIMM_A_SIZE_MASK \| MAD_DIMM_B_SIZE_MASK;
		@@ -611,7 +611,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
		swizzle_y = I915_BIT_6_SWIZZLE_NONE;
		} else if (IS_MOBILE(dev_priv) \|\|
		IS_I915G(dev_priv) \|\| IS_I945G(dev_priv)) {
		uint32_t dcc;
		u32 dcc;

		/* On 9xx chipsets, channel interleave by the CPU is
		* determined by DCC. For single-channel, neither the CPU

+5 −5

Original line number	Diff line number	Diff line
		@@ -1082,7 +1082,7 @@ i915_error_object_create(struct drm_i915_private *i915,
		/* The error capture is special as tries to run underneath the normal
		* locking rules - so we use the raw version of the i915_gem_active lookup.
		*/
		static inline uint32_t
		static inline u32
		__active_get_seqno(struct i915_gem_active *active)
		{
		struct i915_request *request;
		@@ -1153,11 +1153,11 @@ static u32 capture_error_bo(struct drm_i915_error_buffer *err,
		*
		* It's only a small step better than a random number in its current form.
		*/
		static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
		static u32 i915_error_generate_code(struct drm_i915_private *dev_priv,
		struct i915_gpu_state *error,
		int *engine_id)
		{
		uint32_t error_code = 0;
		u32 error_code = 0;
		int i;

		/* IPEHR would be an ideal way to detect errors, as it's the gross

+1 −1

Original line number	Diff line number	Diff line
		@@ -3021,7 +3021,7 @@ static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
		(addr >= 0x182300 && addr <= 0x1823A4);
		}

		static uint32_t mask_reg_value(u32 reg, u32 val)
		static u32 mask_reg_value(u32 reg, u32 val)
		{
		/* HALF_SLICE_CHICKEN2 is programmed with a the
		* WaDisableSTUnitPowerOptimization workaround. Make sure the value

+2 −2

Original line number	Diff line number	Diff line
		@@ -117,14 +117,14 @@
		*/

		typedef struct {
		uint32_t reg;
		u32 reg;
		} i915_reg_t;

		#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })

		#define INVALID_MMIO_REG _MMIO(0)

		static inline uint32_t i915_mmio_reg_offset(i915_reg_t reg)
		static inline u32 i915_mmio_reg_offset(i915_reg_t reg)
		{
		return reg.reg;
		}