drm/amd/display: DSC Slice height debugfs write entry (734e4c97) · Commits · 戴 / test

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+6 −1

Original line number	Diff line number	Diff line
		@@ -4670,9 +4670,14 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
		/* Overwrite the stream flag if DSC is enabled through debugfs */
		if (aconnector->dsc_settings.dsc_clock_en)
		stream->timing.flags.DSC = 1;

		if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_slice_width)
		stream->timing.dsc_cfg.num_slices_h = DIV_ROUND_UP(stream->timing.h_addressable,
		aconnector->dsc_settings.dsc_slice_width);

		if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_slice_height)
		stream->timing.dsc_cfg.num_slices_v = DIV_ROUND_UP(stream->timing.v_addressable,
		aconnector->dsc_settings.dsc_slice_height);
		}
		#endif
		}

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -345,6 +345,7 @@ struct amdgpu_display_manager {
		struct dsc_preferred_settings {
		bool dsc_clock_en;
		uint32_t dsc_slice_width;
		uint32_t dsc_slice_height;
		};

		struct amdgpu_dm_connector {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

+93 −0

Original line number	Diff line number	Diff line
		@@ -1274,6 +1274,22 @@ done:
		return size;
		}

		/* function: read DSC slice height parameter on the connector
		*
		* The read function: dp_dsc_slice_height_read
		* returns dsc slice height used in the current configuration
		* The return is an integer: 0 or other positive number
		*
		* Access the status with the following command:
		*
		* cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
		*
		* 0 - means that DSC is disabled
		*
		* Any other number more than zero represents the
		* slice height currently used by DSC in pixels
		*
		*/
		static ssize_t dp_dsc_slice_height_read(struct file f, char __user buf,
		size_t size, loff_t *pos)
		{
		@@ -1331,6 +1347,82 @@ static ssize_t dp_dsc_slice_height_read(struct file f, char __user buf,
		return result;
		}

		/* function: write DSC slice height parameter
		*
		* The write function: dp_dsc_slice_height_write
		* overwrites automatically generated DSC configuration
		* of slice height.
		*
		* The user has to write the slice height divisible by the
		* picture height.
		*
		* Also the user has to write height in hexidecimal
		* rather than in decimal.
		*
		* Writing DSC settings is done with the following command:
		* - To force overwrite slice height (example sets to 128 pixels):
		*
		* echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
		*
		* - To stop overwriting and let driver find the optimal size,
		* set the height to zero:
		*
		* echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
		*
		*/
		static ssize_t dp_dsc_slice_height_write(struct file f, const char __user buf,
		size_t size, loff_t *pos)
		{
		struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
		struct pipe_ctx *pipe_ctx;
		int i;
		char *wr_buf = NULL;
		uint32_t wr_buf_size = 42;
		int max_param_num = 1;
		uint8_t param_nums = 0;
		long param[1] = {0};

		if (size == 0)
		return -EINVAL;

		wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);

		if (!wr_buf) {
		DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
		return -ENOSPC;
		}

		if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
		(long *)param, buf,
		max_param_num,
		&param_nums)) {
		kfree(wr_buf);
		return -EINVAL;
		}

		if (param_nums <= 0) {
		DRM_DEBUG_DRIVER("user data not be read\n");
		kfree(wr_buf);
		return -EINVAL;
		}

		for (i = 0; i < MAX_PIPES; i++) {
		pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
		if (pipe_ctx && pipe_ctx->stream &&
		pipe_ctx->stream->link == aconnector->dc_link)
		break;
		}

		if (!pipe_ctx \|\| !pipe_ctx->stream)
		goto done;

		aconnector->dsc_settings.dsc_slice_height = param[0];

		done:
		kfree(wr_buf);
		return size;
		}

		static ssize_t dp_dsc_bits_per_pixel_read(struct file f, char __user buf,
		size_t size, loff_t *pos)
		{
		@@ -1640,6 +1732,7 @@ static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
		static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
		.owner = THIS_MODULE,
		.read = dp_dsc_slice_height_read,
		.write = dp_dsc_slice_height_write,
		.llseek = default_llseek
		};

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -452,6 +452,7 @@ struct dsc_mst_fairness_params {
		struct drm_dp_mst_port *port;
		bool clock_overwrite;
		uint32_t slice_width_overwrite;
		uint32_t slice_height_overwrite;
		};

		struct dsc_mst_fairness_vars {
		@@ -490,6 +491,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p
		params[i].timing->dsc_cfg.num_slices_h = DIV_ROUND_UP(
		params[i].timing->h_addressable,
		params[i].slice_width_overwrite);

		if (params[i].slice_height_overwrite)
		params[i].timing->dsc_cfg.num_slices_v = DIV_ROUND_UP(
		params[i].timing->v_addressable,
		params[i].slice_height_overwrite);
		} else {
		params[i].timing->flags.DSC = 0;
		}
		@@ -707,6 +713,7 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
		if (params[count].clock_overwrite)
		debugfs_overwrite = true;
		params[count].slice_width_overwrite = aconnector->dsc_settings.dsc_slice_width;
		params[count].slice_height_overwrite = aconnector->dsc_settings.dsc_slice_height;
		params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported;
		dc_dsc_get_policy_for_timing(params[count].timing, &dsc_policy);
		if (!dc_dsc_compute_bandwidth_range(

Admin message