Commit 73180f85 authored by Mattias Nilsson's avatar Mattias Nilsson Committed by Samuel Ortiz
Browse files

mfd: Move to the new db500 PRCMU API 



Now that we have a shared API between the DB8500 and DB5500
PRCMU's, switch to using this neutral API instead. We delete the
parts of db8500-prcmu.h that is now PRCMU-neutral, and calls will
be diverted to respective driver. Common registers are in
dbx500-prcmu-regs.h and common accessors and defines in
<linux/mfd/dbx500-prcmu.h> This way we get a a lot more
abstraction and code reuse.

Signed-off-by: default avatarMattias Nilsson <mattias.i.nilsson@stericsson.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
parent fea799e3

arch/arm/mach-ux500/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ void __init ux500_init_irq(void) 
	if (cpu_is_u5500())

		db5500_prcmu_early_init();

	if (cpu_is_u8500())

		prcmu_early_init();

		db8500_prcmu_early_init();

	clk_init();

}

drivers/cpufreq/db8500-cpufreq.c

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <linux/cpufreq.h>

#include <linux/delay.h>

#include <linux/slab.h>

#include <linux/mfd/db8500-prcmu.h>

#include <linux/mfd/dbx500-prcmu.h>

#include <mach/id.h>



static struct cpufreq_frequency_table freq_table[] = {

drivers/mfd/db5500-prcmu-regs.h

deleted100644 → 0
+0 −115
Original line number Diff line number Diff line 
/*

 * Copyright (C) STMicroelectronics 2009

 * Copyright (C) ST-Ericsson SA 2010

 *

 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>

 * Author: Sundar Iyer <sundar.iyer@stericsson.com>

 *

 * License Terms: GNU General Public License v2

 *

 * PRCM Unit registers

 */



#ifndef __MACH_PRCMU_REGS_H

#define __MACH_PRCMU_REGS_H



#include <mach/hardware.h>



#define PRCM_ARM_PLLDIVPS	(_PRCMU_BASE + 0x118)

#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE		0x3f

#define PRCM_ARM_PLLDIVPS_MAX_MASK		0xf



#define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)

#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3	0x2



#define PRCM_ARM_CHGCLKREQ	(_PRCMU_BASE + 0x114)

#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ	0x1



#define PRCM_PLLARM_ENABLE	(_PRCMU_BASE + 0x98)

#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE	0x1

#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON	0x100



#define PRCM_ARMCLKFIX_MGT	(_PRCMU_BASE + 0x0)

#define PRCM_A9_RESETN_CLR	(_PRCMU_BASE + 0x1f4)

#define PRCM_A9_RESETN_SET	(_PRCMU_BASE + 0x1f0)

#define PRCM_ARM_LS_CLAMP	(_PRCMU_BASE + 0x30c)

#define PRCM_SRAM_A9		(_PRCMU_BASE + 0x308)



/* ARM WFI Standby signal register */

#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)

#define PRCM_IOCR		(_PRCMU_BASE + 0x310)

#define PRCM_IOCR_IOFORCE			0x1



/* CPU mailbox registers */

#define PRCM_MBOX_CPU_VAL	(_PRCMU_BASE + 0x0fc)

#define PRCM_MBOX_CPU_SET	(_PRCMU_BASE + 0x100)

#define PRCM_MBOX_CPU_CLR	(_PRCMU_BASE + 0x104)



/* Dual A9 core interrupt management unit registers */

#define PRCM_A9_MASK_REQ	(_PRCMU_BASE + 0x328)

#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ	0x1



#define PRCM_A9_MASK_ACK	(_PRCMU_BASE + 0x32c)

#define PRCM_ARMITMSK31TO0	(_PRCMU_BASE + 0x11c)

#define PRCM_ARMITMSK63TO32	(_PRCMU_BASE + 0x120)

#define PRCM_ARMITMSK95TO64	(_PRCMU_BASE + 0x124)

#define PRCM_ARMITMSK127TO96	(_PRCMU_BASE + 0x128)

#define PRCM_POWER_STATE_VAL	(_PRCMU_BASE + 0x25C)

#define PRCM_ARMITVAL31TO0	(_PRCMU_BASE + 0x260)

#define PRCM_ARMITVAL63TO32	(_PRCMU_BASE + 0x264)

#define PRCM_ARMITVAL95TO64	(_PRCMU_BASE + 0x268)

#define PRCM_ARMITVAL127TO96	(_PRCMU_BASE + 0x26C)



#define PRCM_HOSTACCESS_REQ	(_PRCMU_BASE + 0x334)

#define ARM_WAKEUP_MODEM	0x1



#define PRCM_ARM_IT1_CLEAR	(_PRCMU_BASE + 0x48C)

#define PRCM_ARM_IT1_VAL	(_PRCMU_BASE + 0x494)

#define PRCM_HOLD_EVT		(_PRCMU_BASE + 0x174)



#define PRCM_ITSTATUS0		(_PRCMU_BASE + 0x148)

#define PRCM_ITSTATUS1		(_PRCMU_BASE + 0x150)

#define PRCM_ITSTATUS2		(_PRCMU_BASE + 0x158)

#define PRCM_ITSTATUS3		(_PRCMU_BASE + 0x160)

#define PRCM_ITSTATUS4		(_PRCMU_BASE + 0x168)

#define PRCM_ITSTATUS5		(_PRCMU_BASE + 0x484)

#define PRCM_ITCLEAR5		(_PRCMU_BASE + 0x488)

#define PRCM_ARMIT_MASKXP70_IT	(_PRCMU_BASE + 0x1018)



/* System reset register */

#define PRCM_APE_SOFTRST	(_PRCMU_BASE + 0x228)



/* Level shifter and clamp control registers */

#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)

#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)



/* PRCMU clock/PLL/reset registers */

#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)

#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)

#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)

#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)

#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)

#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)

#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)

#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)

#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)

#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)

#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)

#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)

#define PRCM_CLKOCR		   (_PRCMU_BASE + 0x1CC)



/* ePOD and memory power signal control registers */

#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)

#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)



/* Debug power control unit registers */

#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)



/* Miscellaneous unit registers */

#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)

#define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)

#define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800

#define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1





#endif /* __MACH_PRCMU__REGS_H */

drivers/mfd/db5500-prcmu.c

+11 −11
Original line number Diff line number Diff line
@@ -20,11 +20,11 @@ 
#include <linux/jiffies.h>

#include <linux/bitops.h>

#include <linux/interrupt.h>

#include <linux/mfd/db5500-prcmu.h>

#include <linux/mfd/dbx500-prcmu.h>

#include <mach/hardware.h>

#include <mach/irqs.h>

#include <mach/db5500-regs.h>

#include "db5500-prcmu-regs.h"

#include "dbx500-prcmu-regs.h"



#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)

#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
@@ -315,31 +315,31 @@ static bool read_mailbox_0(void) 
		r = false;

		break;

	}

	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);

	return r;

}



static bool read_mailbox_1(void)

{

	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);

	return false;

}



static bool read_mailbox_2(void)

{

	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);

	return false;

}



static bool read_mailbox_3(void)

{

	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);

	return false;

}



static bool read_mailbox_4(void)

{

	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);

	return false;

}
@@ -360,19 +360,19 @@ static bool read_mailbox_5(void) 
		print_unknown_header_warning(5, header);

		break;

	}

	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);

	return false;

}



static bool read_mailbox_6(void)

{

	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);

	return false;

}



static bool read_mailbox_7(void)

{

	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);

	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);

	return false;

}
@@ -434,7 +434,7 @@ int __init db5500_prcmu_init(void) 
		return -ENODEV;



	/* Clean up the mailbox interrupts after pre-kernel code. */

	writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR);

	writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);



	r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,

		prcmu_irq_thread_fn, 0, "prcmu", NULL);

drivers/mfd/db8500-prcmu.c

+23 −23
Original line number Diff line number Diff line
@@ -27,14 +27,14 @@ 
#include <linux/platform_device.h>

#include <linux/uaccess.h>

#include <linux/mfd/core.h>

#include <linux/mfd/db8500-prcmu.h>

#include <linux/mfd/dbx500-prcmu.h>

#include <linux/regulator/db8500-prcmu.h>

#include <linux/regulator/machine.h>

#include <mach/hardware.h>

#include <mach/irqs.h>

#include <mach/db8500-regs.h>

#include <mach/id.h>

#include "db8500-prcmu-regs.h"

#include "dbx500-prcmu-regs.h"



/* Offset for the firmware version within the TCPM */

#define PRCMU_FW_VERSION_OFFSET 0xA4
@@ -507,7 +507,7 @@ static struct { 
} prcmu_version;





int prcmu_enable_dsipll(void)

int db8500_prcmu_enable_dsipll(void)

{

	int i;

	unsigned int plldsifreq;
@@ -542,7 +542,7 @@ int prcmu_enable_dsipll(void) 
	return 0;

}



int prcmu_disable_dsipll(void)

int db8500_prcmu_disable_dsipll(void)

{

	/* Disable dsi pll */

	writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
@@ -551,7 +551,7 @@ int prcmu_disable_dsipll(void) 
	return 0;

}



int prcmu_set_display_clocks(void)

int db8500_prcmu_set_display_clocks(void)

{

	unsigned long flags;

	unsigned int dsiclk;
@@ -734,7 +734,7 @@ unlock_and_return: 
	return r;

}



int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)

int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)

{

	unsigned long flags;
@@ -791,7 +791,7 @@ static void config_wakeups(void) 
	last_abb_events = abb_events;

}



void prcmu_enable_wakeups(u32 wakeups)

void db8500_prcmu_enable_wakeups(u32 wakeups)

{

	unsigned long flags;

	u32 bits;
@@ -812,7 +812,7 @@ void prcmu_enable_wakeups(u32 wakeups) 
	spin_unlock_irqrestore(&mb0_transfer.lock, flags);

}



void prcmu_config_abb_event_readout(u32 abb_events)

void db8500_prcmu_config_abb_event_readout(u32 abb_events)

{

	unsigned long flags;
@@ -824,7 +824,7 @@ void prcmu_config_abb_event_readout(u32 abb_events) 
	spin_unlock_irqrestore(&mb0_transfer.lock, flags);

}



void prcmu_get_abb_event_buffer(void __iomem **buf)

void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)

{

	if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)

		*buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
@@ -833,13 +833,13 @@ void prcmu_get_abb_event_buffer(void __iomem **buf) 
}



/**

 * prcmu_set_arm_opp - set the appropriate ARM OPP

 * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP

 * @opp: The new ARM operating point to which transition is to be made

 * Returns: 0 on success, non-zero on failure

 *

 * This function sets the the operating point of the ARM.

 */

int prcmu_set_arm_opp(u8 opp)

int db8500_prcmu_set_arm_opp(u8 opp)

{

	int r;
@@ -870,11 +870,11 @@ int prcmu_set_arm_opp(u8 opp) 
}



/**

 * prcmu_get_arm_opp - get the current ARM OPP

 * db8500_prcmu_get_arm_opp - get the current ARM OPP

 *

 * Returns: the current ARM OPP

 */

int prcmu_get_arm_opp(void)

int db8500_prcmu_get_arm_opp(void)

{

	return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);

}
@@ -1024,14 +1024,14 @@ int prcmu_release_usb_wakeup_state(void) 
}



/**

 * prcmu_set_epod - set the state of a EPOD (power domain)

 * db8500_prcmu_set_epod - set the state of a EPOD (power domain)

 * @epod_id: The EPOD to set

 * @epod_state: The new EPOD state

 *

 * This function sets the state of a EPOD (power domain). It may not be called

 * from interrupt context.

 */

int prcmu_set_epod(u16 epod_id, u8 epod_state)

int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)

{

	int r = 0;

	bool ram_retention = false;
@@ -1221,14 +1221,14 @@ static int request_reg_clock(u8 clock, bool enable) 
}



/**

 * prcmu_request_clock() - Request for a clock to be enabled or disabled.

 * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.

 * @clock:      The clock for which the request is made.

 * @enable:     Whether the clock should be enabled (true) or disabled (false).

 *

 * This function should only be used by the clock implementation.

 * Do not use it from any other place!

 */

int prcmu_request_clock(u8 clock, bool enable)

int db8500_prcmu_request_clock(u8 clock, bool enable)

{

	if (clock < PRCMU_NUM_REG_CLOCKS)

		return request_reg_clock(clock, enable);
@@ -1240,7 +1240,7 @@ int prcmu_request_clock(u8 clock, bool enable) 
		return -EINVAL;

}



int prcmu_config_esram0_deep_sleep(u8 state)

int db8500_prcmu_config_esram0_deep_sleep(u8 state)

{

	if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||

	    (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
@@ -1515,18 +1515,18 @@ unlock_and_return: 
	mutex_unlock(&mb0_transfer.ac_wake_lock);

}



bool prcmu_is_ac_wake_requested(void)

bool db8500_prcmu_is_ac_wake_requested(void)

{

	return (atomic_read(&ac_wake_req_state) != 0);

}



/**

 * prcmu_system_reset - System reset

 * db8500_prcmu_system_reset - System reset

 *

 * Saves the reset reason code and then sets the APE_SOFRST register which

 * Saves the reset reason code and then sets the APE_SOFTRST register which

 * fires interrupt to fw

 */

void prcmu_system_reset(u16 reset_code)

void db8500_prcmu_system_reset(u16 reset_code)

{

	writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));

	writel(1, PRCM_APE_SOFTRST);
@@ -1782,7 +1782,7 @@ static struct irq_chip prcmu_irq_chip = { 
	.irq_unmask	= prcmu_irq_unmask,

};



void __init prcmu_early_init(void)

void __init db8500_prcmu_early_init(void)

{

	unsigned int i;

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