Commit 7315b933 authored Oct 30, 2013 by Antti Palosaari Committed by Mauro Carvalho Chehab Oct 31, 2013

[media] r820t: add support for R828D

Small changes in order to support tuner version R828D @ 16 MHz clock.
There was 'vco_fine_tune' check, which seems to adjust synthesizer
output divider (mixer dix / LO div / Rout) by one. R828D seems to
return vco_fine_tune=1 every time and that condition causes tuning
fail as output divider was increased by one.
Resolve problem by skipping whole condition in case of R828D tuner.
Just to mention, other tuner, R820T, seems to return 2 here.
Synthesizer maximum frequency check was hard coded to check synthesizer N
and thus worked correctly only for clock frequencies around 30 MHz.
As whole test is quite useless in any case, I removed it totally.

Signed-off-by: Antti Palosaari <crope@iki.fi>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

parent 4f7c09b9

drivers/media/tuners/r820t.c

+13 −9

Original line number	Diff line number	Diff line
		@@ -612,10 +612,19 @@ static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,

		vco_fine_tune = (data[4] & 0x30) >> 4;

		tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
		mix_div, div_num, vco_fine_tune);

		/*
		* XXX: R828D/16MHz seems to have always vco_fine_tune=1.
		* Due to that, this calculation goes wrong.
		*/
		if (priv->cfg->rafael_chip != CHIP_R828D) {
		if (vco_fine_tune > VCO_POWER_REF)
		div_num = div_num - 1;
		else if (vco_fine_tune < VCO_POWER_REF)
		div_num = div_num + 1;
		}

		rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
		if (rc < 0)
		@@ -637,11 +646,6 @@ static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
		vco_fra = pll_ref * 129 / 128;
		}

		if (nint > 63) {
		tuner_info("No valid PLL values for %u kHz!\n", freq);
		return -EINVAL;
		}

		ni = (nint - 13) / 4;
		si = nint - 4 * ni - 13;

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